32Mx72 bits
Registered DDR SDRAM DIMM
HYMD232G726B(L)F8-J
DESCRIPTION
Preliminary
Hynix HYMD232G726B(L)F8-J series is registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory
Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix HYMD232G726B(L)F8-J series
consists of nine 32Mx8 DDR SDRAM in FBGA packages on a 184pin glass-epoxy substrate. Hynix
HYMD232G726B(L)F8-J series provide a high performance 8-byte interface in 5.25" width form factor of industry stan-
dard. It is suitable for easy interchange and addition.
Hynix HYMD232G726B(L)F8-J series is designed for high speed of up to 166MHz and offers fully synchronous opera-
tions referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD232G726B(L)F8-J series incorporates SPD(serial presence detect). Serial presence detect function is imple-
mented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM
type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
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256MB (32Mx72) Registered DDR DIMM based on
32Mx8 DDR SDRAM
JEDEC Standard 184-pin dual in-line memory module
(DIMM)
Error Check Correction (ECC) Capability
Registered inputs with one-clock delay
Phase-lock loop (PLL) clock driver to reduce loading
2.5V +/- 0.2V VDD and VDDQ Power supply
All inputs and outputs are compatible with SSTL_2
interface
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Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz/166MHz
Programmable CAS Latency 2 / 2.5 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
tRAS Lock-out function supported
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
HYMD232G726B(L)F8-J
Power Supply
V
DD
=2.5V
V
DDQ
=2.5V
Clock Frequency
166MHz (*DDR333)
Interface
SSTL_2
Form Factor
184pin Registered DIMM
5.25 x 1.125 x 0.15 inch
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / Mar. 2004
1
HYMD232G726B(L)F8-J
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Voltage on V
DDQ
relative to V
SS
Output Short Circuit Current
Power Dissipation
Soldering Temperature Þ Time
T
A
T
STG
V
IN
, V
OUT
V
DD
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
18
260 / 10
Rating
o
o
Unit
C
C
V
V
V
mA
W
o
C / Sec
Note :
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Termination Voltage
Reference Voltage
V
DD
V
DDQ
V
IH
V
IL
V
TT
V
REF
Symbol
Min
2.3
2.3
V
REF
+ 0.15
-0.3
V
REF
- 0.04
0.49*VDDQ
Typ.
2.5
2.5
-
-
V
REF
0.5*VDDQ
Max
2.7
2.7
V
DDQ
+ 0.3
V
REF
- 0.15
V
REF
+ 0.04
0.51*VDDQ
Unit
V
V
V
V
V
V
3
2
1
Note
Note :
1. V
DDQ
must not exceed the level of V
DD
.
2. V
IL
(min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of V
REF
is approximately equal to 0.5V
DDQ
.
AC OPERATING CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
Input Crossing Point Voltage, CK and /CK inputs
Symbol
V
IH(AC)
V
IL(AC)
V
ID(AC)
V
IX(AC)
0.7
0.5*V
DDQ
-0.2
Min
V
REF
+ 0.31
V
REF
- 0.31
V
DDQ
+ 0.6
0.5*V
DDQ
+0.2
Max
Unit
V
V
V
V
1
2
Note
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.1 / Mar. 2004
4
HYMD232G726B(L)F8-J
AC OPERATING TEST CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to VSS = 0V)
Parameter
Reference Voltage
Termination Voltage
AC Input High Level Voltage (V
IH
, min)
AC Input Low Level Voltage (V
IL
, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Input Signal maximum peak swing
Input minimum Signal Slew Rate
Termination Resistor (R
T
)
Series Resistor (R
S
)
Output Load Capacitance for Access Time Measurement (C
L
)
Value
V
DDQ
x 0.5
V
DDQ
x 0.5
V
REF
+ 0.31
V
REF
- 0.31
V
REF
V
TT
1.5
1
50
25
30
Unit
V
V
V
V
V
V
V
V/ns
Ω
Ω
pF
Rev. 0.1 / Mar. 2004
5
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