240pin DDR3 SDRAM Registered DIMM
DDR3 SDRAM
Unbuffered DIMMs
Based on 2Gb B-Die
HMT325U6BFR8C
HMT325U7BFR8C
HMT351U6BFR8C
HMT351U7BFR8C
*
Hynix Semiconductor reserves the right to change products or specifications without notice.
Rev. 0.2 / Feb. 2010
1
Description
Hynix Unbuffered DDR3 SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-Line
Memory Modules) are low power, high-speed operation memory modules that use Hynix DDR3 SDRAM
devices. These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems
such as PCs and workstations.
Features
• VDD=1.5V +/- 0.075V
• VDDQ=1.5V +/- 0.075V
• VDDSPD=3.0V to 3.6V
• Functionality and operations comply with the
DDR3 SDRAM datasheet
• 8 internal banks
• Data transfer rates: PC3-10600, PC3-8500, or
PC3-6400
• Bi-directional Differential Data Strobe
• 8 bit pre-fetch
• Burst Length (BL) switch on-the-fly: BL 8 or BC
(Burst Chop) 4
• Supports ECC error correction and detection
• On Die Termination (ODT) supported
• Temperature sensor with integrated SPD (Serial
Presence Detect) EEPROM
• RoHS compliant
* This product is in compliance with the RoHS directive.
Ordering Information
Part Number
HMT325U6BFR8C-G7/H9/PB
HMT325U7BFR8C-G7/H9/PB
HMT351U6BFR8C-G7/H9/PB
HMT351U7BFR8C-G7/H9/PB
Rev. 0.2 / Feb. 2010
Density
2GB
2GB
4GB
4GB
Organization
256Mx64
256Mx72
512Mx64
512Mx72
Component Composition
256Mx8(H5TQ2G83BFR)*8
256Mx8(H5TQ2G83BFR)*9
256Mx8(H5TQ2G83BFR)*16
256Mx8(H5TQ2G83BFR)*18
# of
ranks
1
1
2
2
FDHS
X
X
X
X
3
Pin Descriptions
Pin Name
A0–A15
BA0–BA2
RAS
CAS
WE
S0–S1
CKE0–CKE1
ODT0–ODT1
DQ0–DQ63
CB0–CB7
DQS0–DQS8
DQS0–DQS8
DM0–DM8
CK0–CK1
CK0–CK1
Description
SDRAM address bus
SDRAM bank select
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
DIMM Rank Select Lines
SDRAM clock enable lines
On-die termination control lines
DIMM memory data bus
DIMM ECC check bits
SDRAM data strobes
(positive line of differential pair)
SDRAM data strobes
(negative line of differential pair)
SDRAM data masks/high data strobes
(x8-based x72 DIMMs)
SDRAM clocks
(positive line of differential pair)
SDRAM clocks
(negative line of differential pair)
Pin Name
SCL
SDA
SA0–SA2
V
DD*
V
DD
Q
*
V
REF
DQ
V
REF
CA
V
SS
V
DDSPD
NC
TEST
RESET
V
TT
RSVD
-
Description
I
2
C serial bus clock for EEPROM
I
2
C serial bus data line for EEPROM
I
2
C slave address select for EEPROM
SDRAM core power supply
SDRAM I/O Driver power supply
SDRAM I/O reference supply
SDRAM command/address reference
supply
Power supply return (ground)
Serial EEPROM positive power supply
Spare pins (no connect)
Memory bus analysis tools
(unused on memory DIMMS)
Set DRAMs to Known State
SDRAM I/O termination supply
Reserved for future use
-
*The V
DD
and V
DD
Q pins are tied common to a single power-plane on these designs
Rev. 0.2 / Feb. 2010
5
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