240pin DDR3 SDRAM Unbuffered DIMMs
DDR3 SDRAM Unbuffered DIMMs
Based on 1Gb A version
HMT164U6AFP(R)6C
HMT112U6AFP(R)8C
HMT112U7AFP(R)8C
HMT125U6AFP(R)8C
HMT125U7AFP(R)8C
** Contents are subject to change without prior notice.
Rev. 0.1 / Dec 2008
1
HMT164U6AFP(R)6C
HMT112U6(7)AFP(R)8C
HMT125U6(7)AFP(R)8C
Revision History
Revision No.
0.01
0.02
0.1
History
Initial draft for internal review
Added IDD & Halogen-free products
Initial Specification Release.
Corrected typo on package ball feature.
Draft Date
Nov. 2007
Mar. 2008
Dec 2008
Remark
Preliminary
Preliminary
Rev. 0.1 / Dec 2008
2
HMT164U6AFP(R)6C
HMT112U6(7)AFP(R)8C
HMT125U6(7)AFP(R)8C
Table of Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Features
1.1.2 Ordering Information
1.2 Speed Grade & Key Parameters
1.3 Address Table
2. Pin Architecture
2.1 Pin Definition
2.2 Input/Output Functional Description
2.3 Pin Assignment
3. Functional Block Diagram
3.1 512MB, 64Mx64 Module(1Rank of x16)
3.2 1GB, 128Mx64 Module(1Rank of x8)
3.3 1GB, 128Mx72 ECC Module(1Rank of x8)
3.4 2GB, 256Mx64 Module(2Rank of x8)
3.5 2GB, 256Mx72 ECC Module(2Rank of x8)
4. Address Mirroring Feature
4.1 DRAM Pin Wiring for Mirroring
5. Absolute Maximum Ratings
5.1 Absolute Maximum DC Ratings
5.2 Operating Temperature Range
6. AC & DC Operating Conditions
6.1 Recommended DC Operating Conditions
6.2 DC & AC Logic Input Levels
6.2.1 For Single-ended Signals
6.2.2 For Differential Signals
6.2.3 Differential Input Cross Point
6.3 Slew Rate Definition
6.3.1 For Ended Input Signals
6.3.2 For Differential Input Signals
6.4 DC & AC Output Buffer Levels
6.4.1 Single Ended DC & AC Output Levels
6.4.2 Differential DC & AC Output Levels
6.4.3 Single Ended Output Slew Rate
6.4.4 Differential Ended Output Slew Rate
6.5 Overshoot/Undershoot Specification
6.6 Input/Output Capacitance & AC Parametrics
6.7 IDD Specifications & Measurement Conditions
7. Electrical Characteristics and AC Timing
7.1 Refresh Parameters by Device Density
7.2 DDR3 Standard speed bins and AC para
8. DIMM Outline Diagram
8.1 512MB, 64Mx64 Module(1Rankx16)
8.2 1GB, 128Mx64 Module(1Rank of x8)
8.3 1GB, 128Mx72 ECC Module(1Rank of x8)
8.4 2GB, 256Mx64 Module(2Rank of x8)
8.5 2GB, 256Mx72 ECC Module(2Rank of x8)
Rev. 0.1 / Dec 2008
3
HMT164U6AFP(R)6C
HMT112U6(7)AFP(R)8C
HMT125U6(7)AFP(R)8C
1. Description
This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb A version. DDR3 SDRAMs in Fine
Ball Grid Array(FBGA) packages on a 240 pin glass-epoxy substrate. This DDR3 Unbuffered DIMM series based on 1Gb
A ver. provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable
for easy interchange and addition.
1.1 Device Features & Ordering Information
1.1.1 Features
• VDD=VDDQ=1.5V
• VDDSPD=3.3V to 3.6V
• Fully differential clock inputs (CK, /CK) operation
• Differential Data Strobe (DQS, /DQS)
• On chip DLL align DQ, DQS and /DQS transition with
CK transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11)
supported
• Programmable additive latency 0, CL-1, and CL-2 sup
ported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8banks
• 8K refresh cycles /64ms
• DDR3 SDRAM Package: JEDEC standard 78ball
FBGA(x4/x8), 96ball FBGA(x16) with support balls
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• Auto Self Refresh supported
• On Die Thermal Sensor supported (JEDEC optional)
Rev. 0.1 / Dec 2008
4
HMT164U6AFP(R)6C
HMT112U6(7)AFP(R)8C
HMT125U6(7)AFP(R)8C
1.1.2 Ordering Information
# of
# of
DRAMs ranks
4
4
8
8
9
9
16
16
18
18
1
1
1
1
1
1
2
2
2
2
Part Name
HMT164U6AFP6C-S6/S5/G8/G7/H9/H8
HMT164U6AFR6C-S6/S5/G8/G7/H9/H8
HMT112U6AFP8C-S6/S5/G8/G7/H9/H8
HMT112U6AFR8C-S6/S5/G8/G7/H9/H8
HMT112U7AFP8C-S6/S5/G8/G7/H9/H8
HMT112U7AFR8C-S6/S5/G8/G7/H9/H8
HMT125U6AFP8C-S6/S5/G8/G7/H9/H8
HMT125U6AFR8C-S6/S5/G8/G7/H9/H8
HMT125U7AFP8C-S6/S5/G8/G7/H9/H8
HMT125U7AFR8C-S6/S5/G8/G7/H9/H8
Density
512MB
512MB
1GB
1GB
1GB
1GB
2GB
2GB
2GB
2GB
Org.
64Mx64
64Mx64
128Mx64
128Mx64
128Mx72
128Mx72
256Mx64
256Mx64
256Mx72
256Mx72
Materials
Lead-free
ECC
None
TS
No
No
No
No
Yes
Yes
No
No
Yes
Yes
Halogen-free None
Lead free
None
Halogen-free None
Lead free
Halogen-free
Lead free
ECC
ECC
None
Halogen-free None
Lead free
Halogen-free
ECC
ECC
Rev. 0.1 / Dec 2008
5
FPGA/CPLD
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