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HMP351S6AFR8C-S6: 产品描述200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 2Gb version A; 产品类别存储存储; 文件大小290KB，共17页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/; 标准

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HMP351S6AFR8C-S6概述

200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 2Gb version A

HMP351S6AFR8C-S6规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	SK Hynix(海力士)
零件包装代码	SODIMM
包装说明	DIMM, DIMM200,24
针数	200
Reach Compliance Code	unknow
ECCN代码	EAR99
访问模式	DUAL BANK PAGE BURST
最长访问时间	0.4 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	400 MHz
I/O 类型	COMMON
JESD-30 代码	R-XZMA-N200
长度	67.6 mm
内存密度	34359738368 bi
内存集成电路类型	DDR DRAM MODULE
内存宽度	64
功能数量	1
端口数量	1
端子数量	200
字数	536870912 words
字数代码	512000000
工作模式	SYNCHRONOUS
最高工作温度	65 °C
最低工作温度
组织	512MX64
输出特性	3-STATE
封装主体材料	UNSPECIFIED
封装代码	DIMM
封装等效代码	DIMM200,24
封装形状	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）	260
电源	1.8 V
认证状态	Not Qualified
刷新周期	8192
自我刷新	YES
最大待机电流	0.192 A
最大压摆率	2.88 mA
最大供电电压 (Vsup)	1.9 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	NO
技术	CMOS
温度等级	COMMERCIAL
端子形式	NO LEAD
端子节距	0.6 mm
端子位置	ZIG-ZAG
处于峰值回流温度下的最长时间	20

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200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 2Gb version A

This Hynix unbuffered Small Outline Dual In-Line Memory Module (DIMM) series consists of 2Gb version A DDR2

SDRAMs in Fine Ball Grid Array (FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 2Gb version A based

Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of indus-

try standard. It is suitable for easy interchange and addition.

FEATURES

•

JEDEC standard Double Data Rate 2 Synchronous

DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power

Supply

•

All inputs and outputs are compatible with SSTL_1.8

interface

•

Posted CAS

Programmable CAS Latency 3,4,5, and 6

OCD (Off-Chip Driver Impedance Adjustment) and

ODT (On-Die Termination)

•

Fully differential clock operations (CK & CK)

•

Programmable Burst Length 4 / 8 with both

sequential and interleave mode

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

Serial presence detect with EEPROM

DDR2 SDRAM Package: 60 ball(x4/8)

67.60 x 30.00 mm form factor

RoHS compliant & Halogen-free

This product is in compliance with the directive pertaining of RoHS.

ORDERING INFORMATION

Part Name

HMP351S6AFR8C-Y5/S5/S6

Density

4GB

Organization

512Mx64

# of

DRAMs

# of

ranks

Materials

Halogen free

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.0 / Dec. 2009

1200pin

Unbuffered DDR2 SDRAM SO-DIMMs

PIN DESCRIPTION

Symbol

Type

Polarity

Cross

Point

Pin Description

The system clock inputs. All address an commands lines are sampled on the cross point

CK[1:0], CK[1:0]

Input

of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is

driven from the clock inputs and output timing for read operations is synchronized to

the input clock.

CKE[1:0]

Input

Active

High

Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when

low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self

Refresh mode.

Enables the associated DDR2 SDRAM command decoder when low and disables the

S[1:0]

Input

Active

Low

Active

Low

command decoder when high. When the command decoder is disabled, new commands

are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is

selected by S1

RAS, CAS, WE

BA[2:0]

ODT[1:0]

Input

Active

High

When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS,

RAS and WE define the operation to be executed by the SDRAM.

Selects which DDR2 SDRAM internal bank of four or eight is activated.

Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2

SDRAM mode register.

During a Bank Activate command cycle, difines the row address when sampled at the

cross point of the rising edge of CK and falling edge of CK. During a Read or Write com-

mand cycle, defines the column address when sampled at the cross point of the rising

edge of CK and falling edge of CK. In addition to the column address, AP is used to

A[9:0], A10/AP,

A[15:11]

Input

invoke autoprecharge operation at the end of the burst read or write cycle. If AP is

high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP

is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in

conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks

will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn

are used to define which bank to precharge.

DQ[63:0]

DM[7:0]

In/Out

Input

Active

High

Data Input/Output pins.

The data write masks, associated with one data byte. In Write mode, DM operates as a

byte mask by allowing input data to be written if it is low but blocks the write operation

if it is high. In Read mode, DM lines have no effect.

The data strobe, associated with one data byte, sourced whit data transfers. In Write

mode, the data strobe is sourced by the controller and is centered in the data window.

DQS[7:0], DQS[7:0] In/Out

Cross

point

In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading

edge of the data window. DQS signals are complements, and timing is relative to the

crosspoint of respective DQS and DQS. If the module is to be operated in single ended

strobe mode, all DQS signals must be tied on the system board to VSS and DDR2

SDRAM mode registers programmed approriately.

, V

SPD,V

SDA

SCL

SA[1:0]

TEST

Supply

In/Out

Input

In/Out

Power supplies for core, I/O, Serial Presense Detect, and ground for the module.

This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A

resister must be connected to V

DD t

o act as a pull up.

This signals is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from SCL to VDD to act as a pull up.

Address pins used to select the Serial Presence Detect base address.

The TEST pin is reserved for bus analysis tools and is not connected on normal memory

modules (SODIMMs).

Rev. 1.0 / Dec. 2009

HMP351S6AFR8C-S6相似产品对比

	HMP351S6AFR8C-S6	HMP351S6AFR8C-S5	HMP351S6AFR8C-Y5
描述	200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 2Gb version A	200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 2Gb version A	200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 2Gb version A
是否Rohs认证	符合	符合	符合
厂商名称	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)
零件包装代码	SODIMM	SODIMM	SODIMM
包装说明	DIMM, DIMM200,24	DIMM, DIMM200,24	DIMM, DIMM200,24
针数	200	200	200
Reach Compliance Code	unknow	unknow	unknow
ECCN代码	EAR99	EAR99	EAR99
访问模式	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
最长访问时间	0.4 ns	0.4 ns	0.45 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	400 MHz	400 MHz	333 MHz
I/O 类型	COMMON	COMMON	COMMON
JESD-30 代码	R-XZMA-N200	R-XZMA-N200	R-XZMA-N200
长度	67.6 mm	67.6 mm	67.6 mm
内存密度	34359738368 bi	34359738368 bi	34359738368 bi
内存集成电路类型	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
内存宽度	64	64	64
功能数量	1	1	1
端口数量	1	1	1
端子数量	200	200	200
字数	536870912 words	536870912 words	536870912 words
字数代码	512000000	512000000	512000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	65 °C	65 °C	65 °C
组织	512MX64	512MX64	512MX64
输出特性	3-STATE	3-STATE	3-STATE
封装主体材料	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
封装代码	DIMM	DIMM	DIMM
封装等效代码	DIMM200,24	DIMM200,24	DIMM200,24
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）	260	260	260
电源	1.8 V	1.8 V	1.8 V
认证状态	Not Qualified	Not Qualified	Not Qualified
刷新周期	8192	8192	8192
自我刷新	YES	YES	YES
最大待机电流	0.192 A	0.192 A	0.192 A
最大压摆率	2.88 mA	2.88 mA	2.64 mA
最大供电电压 (Vsup)	1.9 V	1.9 V	1.9 V
最小供电电压 (Vsup)	1.7 V	1.7 V	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V
表面贴装	NO	NO	NO
技术	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子形式	NO LEAD	NO LEAD	NO LEAD
端子节距	0.6 mm	0.6 mm	0.6 mm
端子位置	ZIG-ZAG	ZIG-ZAG	ZIG-ZAG
处于峰值回流温度下的最长时间	20	20	20

HMP351S6AFR8C-S6

HMP351S6AFR8C-S6概述

HMP351S6AFR8C-S6规格参数

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