64K x 32
3.3V Synchronous SRAM
Pipelined Outputs
Burst Counter, Single Cycle Deselect
Features
◆
◆
IDT71V632
◆
◆
◆
◆
◆
◆
◆
64K x 32 memory configuration
Supports high system speed:
Commercial:
– A4 4.5ns clock access time (117 MHz)
Commercial and Industrial:
– 5 5ns clock access time (100 MHz)
– 6 6ns clock access time (83 MHz)
– 7 7ns clock access time (66 MHz)
Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC64K32D7LG-XX)
LBO
input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
Operates with a single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP)
Green parts available, see ordering information
Description
Pin Description Summary
A
0
–A
15
CE
CS
0
,
CS
1
OE
GW
BWE
BW
1,
BW
2,
BW
3,
BW
4
CLK
ADV
ADSC
ADSP
LBO
ZZ
I/O
0
–I/O
31
V
DD
, V
DDQ
V
SS
, V
SSQ
Ad d re ss Inp uts
Chip Enab le
Chip s Se le cts
Outp ut Enab le
Glo b al Write Enab le
Byte Write Enab le
Ind ivid ual Byte Write Se le cts
Clo ck
Burst Ad d re ss Ad vance
Ad d re ss Status (Cache Co ntro lle r)
Ad d re ss Status (Pro ce sso r)
Line ar / Inte rle ave d Burst Ord e r
S le e p Mo d e
Data Inp ut/Outp ut
3.3V
Array Gro und , I/O Gro und
The IDT71V632 is a 3.3V high-speed SRAM organized as 64K x 32
with full support of the Pentium™ and PowerPC™ processor interfaces.
The pipelined burst architecture provides cost-effective 3-1-1-1 second-
ary cache performance for processors up to 117MHz.
The IDT71V632 SRAM contains write, data, address, and control
registers. Internal logic allows the SRAM to generate a self-timed write
based upon a decision which can be left until the extreme end of the write
cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V632 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address counter
accepts the first cycle address from the processor, initiating the access
sequence. The first cycle of output data will be pipelined for one cycle before
it is available on the next rising clock edge. If burst mode operation is
selected (ADV=LOW), the subsequent three cycles of output data will be
available to the user on the next three rising clock edges. The order of these
three addresses will be defined by the internal burst counter and the
LBO
input pin.
The IDT71V632 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board density
in both desktop and notebook applications.
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
I/O
Po we r
Po we r
Synchro no us
Synchro no us
Synchro no us
Asynchro no us
Synchro no us
Synchro no us
Synchro no us
N/A
Synchro no us
Synchro no us
Synchro no us
DC
Asynchro no us
Synchro no us
N/A
N/A
3619 tb l 01
Pentium processor is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
FEBRUARY 2017
1
DSC-3619/09
©2017 Integrated Device Technology, Inc.
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definitions
(1)
Symbol
A
0
–A
15
ADSC
Pin Function
Ad d re ss Inp uts
Ad d re ss Status
(Cache Co ntro lle r)
I/O
I
I
Active
N/A
LOW
Description
Synchro no us Ad d re ss inp uts. The ad d re ss re g iste r is trig g e re d b y a co mb inatio n
o f the rising e d g e o f CLK and
ADSC
Lo w o r
ADSP
Lo w and
CE
Lo w.
Synchro no us Ad d re ss Status fro m Cache Co ntro lle r.
ADSC
is an active LOW
inp ut that is use d to lo ad the ad d re ss re g iste rs with ne w ad d re sse s.
ADSC
is
NOT GATED b y
CE
.
Synchro no us Ad d re ss Status fro m Pro ce sso r.
ADSP
is an active LOW inp ut that
is use d to lo ad the ad d re ss re g iste rs with ne w ad d re sse s.
ADSP
is g ate d b y
CE
.
Synchro no us Ad d re ss Ad vance .
ADV
is an active LOW inp ut that is use d to
ad vance the inte rnal b urst co unte r, co ntro lling b urst acce ss afte r the initial
ad d re ss is lo ad e d . Whe n this inp ut is HIGH the b urst co unte r is no t incre me nte d ;
that is, the re is no ad d re ss ad vance .
Synchro no us b yte write e nab le g ate s the b yte write inp uts
BW
1
–
BW
4
. If
BWE
is
LOW at the rising e d g e o f CLK the n
BW
X
inp uts are p asse d to the ne xt stag e in
the circuit. A b yte write can still b e b lo cke d if
ADSP
is LOW at the rising e d g e o f
CLK. If
ADSP
is HIGH and
BW
X
is LOW at the rising e d g e o f CLK the n d ata will
b e writte n to the SRAM. If
BWE
is HIGH the n the b yte write inp uts are b lo cke d
and o nly
GW
can initiate a write cycle .
Synchro no us b yte write e nab le s.
BW
1
co ntro ls I/O(7:0),
BW
2
co ntro ls I/O(15:8),
e tc. Any active b yte write cause s all o utp uts to b e d isab le d .
ADSP
LOW
d isab le s all b yte write s.
BW
1
–
BW
4
must me e t sp e cifie d se tup and ho ld time s
with re sp e ct to CLK.
Synchro no us chip e nab le .
CE
is use d with CS
0
and
CS
1
to e nab le the
IDT71V632.
CE
also g ate s
ADSP
.
This is the clo ck inp ut. All timing re fe re nce s fo r the d e vice are mad e with re sp e ct
to this inp ut.
Synchro no us active HIGH chip se le ct. CS
0
is use d with
CE
and
CS
1
to e nab le
the chip .
Synchro no us active LOW chip se le ct.
CS
1
is use d with
CE
and CS
0
to e nab le
the chip .
Synchro no us g lo b al write e nab le . This inp ut will write all fo ur 8-b it d ata b yte s
whe n LOW o n the rising e d g e o f CLK.
GW
sup e rce d e s ind ivid ual b yte write
e nab le s.
Synchro no us d ata inp ut/o utp ut (I/O) p ins. Bo th the d ata inp ut p ath and d ata o utp ut
p ath are re g iste re d and trig g e re d b y the rising e d g e o f CLK.
Asynchro no us b urst o rd e r se le ctio n DC inp ut. Whe n
LBO
is HIGH the Inte rle ave d
(Inte l) b urst se q ue nce is se le cte d . Whe n
LBO
is LOW the Line ar (Po we rPC) b urst
se q ue nce is se le cte d .
LBO
is a static DC inp ut and must no t chang e state while
the d e vice is o p e rating .
Asynchro no us o utp ut e nab le . Whe n
OE
is LOW the d ata o utp ut d rive rs are
e nab le d o n the I/O p ins if the chip is also se le cte d . Whe n
OE
is HIGH the I/O
p ins are in a hig h-imp e d e nce state .
3.3V co re p o we r sup p ly inp uts.
3.3V I/O p o we r sup p ly inp uts.
Co re g ro und p ins.
I/O g ro und p ins.
NC p ins are no t e le ctrically co nne cte d to the chip .
Asynchro no us sle e p mo d e inp ut. ZZ HIGH will g ate the CLK inte rnally and p o we r
d o wn the IDT71V632 to its lo we st p o we r co nsump tio n le ve l. Data re te ntio n is
g uarante e d in Sle e p Mo d e .
3619 tb l 02
ADSP
Ad d re ss Status
(Pro ce sso r)
Burst Ad d re ss Ad vance
I
LOW
ADV
I
LOW
BWE
Byte Write Enab le
I
LOW
BW
1
–
BW
4
Ind ivid ual Byte
Write Enab le s
I
LOW
CE
CLK
CS
0
CS
1
Chip Enab le
Clo ck
Chip Se le ct 0
Chip Se le ct 1
I
I
I
I
LOW
N/A
HIGH
LOW
GW
Glo b al Write Enab le
I
LOW
I/O
0
–I/O
31
LBO
Data Inp ut/Outp ut
Line ar Burst Ord e r
I/O
I
N/A
LOW
OE
Outp ut Enab le
I
LOW
V
DD
V
DDQ
V
SS
V
SSQ
NC
ZZ
Po we r Sup p ly
Po we r Sup p ly
Gro und
Gro und
No Co nne ct
S le e p Mo d e
N/A
N/A
N/A
N/A
N/A
I
N/A
N/A
N/A
N/A
N/A
HIGH
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
ADV
CE
Burst
Sequence
INTERNAL
ADDRESS
CLK
ADSC
ADSP
CLK EN
ADDRESS
REGISTER
Byte 1
Write Register
Binary
Counter
CLR
2
Burst
Logic
16
A
0
*
A
1
*
Q0
Q1
64K x 32
BIT
MEMORY
ARRAY
.
32
2
A
0
, A
1
16
A
2
–A
15
32
A
0
–A
15
GW
BWE
BW
1
Byte 1
Write Driver
Byte 2
Write Register
8
Byte 2
Write Driver
BW
2
Byte 3
Write Register
8
Byte 3
Write Driver
BW
3
Byte 4
Write Register
8
Byte 4
Write Driver
BW
4
8
OUTPUT
REGISTER
CE
CS0
CS
1
D
Q
Enable
Register
CLK EN
DATA INPUT
REGISTER
ZZ
Powerdown
D
Q
Enable
Delay
Register
OE
OUTPUT
BUFFER
OE
32
I/O
0
–I/O
31
3619 drw 01
6.42
3
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
V
TERM
T
A
T
BIAS
T
STG
P
T
I
OUT
(3)
Rating
Te rminal Vo ltag e with
Re sp e ct to GND
Te rminal Vo ltag e with
Re sp e ct to GND
Op e rating Te mp e rature
Te mp e rature Und e r Bias
Sto rag e Te mp e rature
Po we r Dissip atio n
DC Outp ut Curre nt
Value
–0.5 to +4.6
–0.5 to V
DD
+0.5
0 to +70
–55 to +125
–55 to +125
1.0
50
Unit
V
V
o
o
o
Recommended Operating
Temperature and Supply Voltage
Grade
Co mme rcial
Ind ustrial
Temperature
0° C to +70° C
–40° C to +85° C
V
SS
0V
0V
V
DD
V
DDQ
3.3V+10/-5% 3.3V+10/-5%
3.3V+10/-5% 3.3V+10/-5%
3619 tb l 03
C
C
C
W
mA
3619 tb l 05
Recommended DC Operating
Conditions
Symbol
V
DD
V
DDQ
V
SS,
V
SSQ
V
IH
V
IH
V
IL
Parameter
Co re Sup p ly Vo ltag e
I/O Sup p ly Vo ltag e
Gro und
Inp ut Hig h Vo ltag e — Inp uts
Inp ut Hig h Vo ltag e — I/O
Inp ut Lo w Vo ltag e
Min.
3.135
3.135
0
2.0
2.0
–0.3
(3)
Max.
3.63
3.63
0
5.0
(1)
V
DDQ
+0.3
(2)
0.8
Unit
V
V
V
V
V
V
3619 tb l 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
DD
, V
DDQ
and Input terminals only.
3. I/O terminals.
Capacitance
Symbol
C
IN
C
I/O
NOTES:
1. V
IH
(max) = 6.0V for pulse width less than t
CYC
/2, once per cycle.
2. V
IH
(max) = V
DDQ
+ 1.0V for pulse width less than t
CYC
/2, once per cycle.
3. V
IL
(min) = –1.0V for pulse width less than t
CYC
/2, once per cycle.
(T
A
= +25°C, f = 1.0MHz, TQFP package)
Parameter
(1)
Inp ut Cap acitance
I/O Cap acitance
Conditions
V
IN
= 3d V
V
OUT
= 3d V
Max.
6
7
Unit
pF
pF
3619 tb l 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.42
4
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
6
A
7
CE
CS
0
BW
4
BW
3
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
NC
I/O
16
I/O
17
V
DDQ
V
SSQ
I/O
18
I/O
19
I/O
20
I/O
21
V
SSQ
V
DDQ
I/O
22
I/O
23
V
DD
/NC
(1)
V
DD
NC
V
SS
I/O
24
I/O
25
V
DDQ
V
SSQ
I/O
26
I/O
27
I/O
28
I/O
29
V
SSQ
V
DDQ
I/O
30
I/O
31
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PKG100
NC
I/O
15
I/O
14
V
DDQ
V
SSQ
I/O
13
I/O
12
I/O
11
I/O
10
V
SSQ
V
DDQ
I/O
9
I/O
8
V
SS
NC
V
DD
ZZ
(2)
I/O
7
I/O
6
V
DDQ
V
SSQ
I/O
5
I/O
4
I/O
3
I/O
2
V
SSQ
V
DDQ
I/O
1
I/O
0
NC
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
NC
3619 drw 02
Top View TQFP
NOTES:
1. Pin 14 can either be directly connected to V
DD
or not connected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
FPGA/CPLD
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