2GB (x72, ECC, DR): 240-Pin DDR3 SDRAM RDIMM
Features
DDR3 SDRAM RDIMM
MT18JSF25672PD – 2GB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• DDR3 functionality and operations supported as
defined in the component data sheet
• 240-pin, registered dual in-line memory module
(RDIMM)
• Fast data transfer rates: PC3-12800, PC3-10600,
PC3-8500, or PC3-6400
• 2GB (256 Meg x 72)
• Vdd = 1.5V ±0.075V
• Vddspd = +3.0V to +3.6V
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Dual rank
• On-board I
2
C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus
Figure 1:
240-Pin RDIMM (MO-269 R/C B)
PCB height: 30.0mm (1.18in)
Options
• Operating temperature
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
• Package
–
240-pin halogen-free DIMM
• Frequency/CAS latency
–
1.25ns @ CL = 11 (DDR3-1600)
–
1.5ns @ CL = 9 (DDR3-1333)
–
1.87ns @ CL = 7 (DDR3-1066)
–
1.87ns @ CL = 8 (DDR3-1066)
2
–
2.5ns @ CL = 5 (DDR3-800)
2
–
2.5ns @ CL = 6 (DDR3-800)
2
1
Marking
None
I
Z
-1G6
-1G4
-1G1
-1G0
-80C
-80B
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. Not recommended for new designs.
Table 1:
Key Timing Parameters
Data Rate (MT/s)
CL = 9
–
1333
–
–
–
–
CL = 8
1066
1066
1066
1066
–
–
CL = 7
–
1066
1066
–
–
–
CL = 6
800
800
800
800
800
800
CL = 5
–
–
–
–
800
–
t
Speed
Industry
Grade Nomenclature CL = 11 CL = 10
-1G6
-1G4
-1G1
-1G0
-80C
-80B
PC3-12800
PC3-10600
PC3-8500
PC3-8500
PC3-6400
PC3-6400
1600
–
–
–
–
–
1333
1333
–
–
–
–
RCD
(ns)
RP
(ns)
13.75
13.5
13.125
15
12.5
15
t
RC
(ns)
48.75
49.5
50.625
52.5
50
52.5
t
13.75
13.5
13.125
15
12.5
15
PDF: 09005aef8382b0a9 / Source: 09005aef8382b0e2
JSF18C256x72PDZ.fm - Rev. A 2/09 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
2GB (x72, ECC, DR): 240-Pin DDR3 SDRAM RDIMM
Features
Table 2:
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
Addressing
2GB
8K
16K A[13:0]
8 BA[2:0]
1Gb (128 Meg x 8)
1K A[9:0]
2 S#[1:0]
Table 3:
Part Numbers and Timing Parameters – 2GB Modules
Base device: MT41J128M8,
1
1Gb DDR3 SDRAM
Module
Density
2GB
2GB
2GB
2GB
2GB
2GB
Module
Bandwidth
12.8 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.25ns/1600 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
11-11-11
9-9-9
7-7-7
8-8-8
5-5-5
6-6-6
Part Number
2
Configuration
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
MT18JSF25672PD(I)Z-1G6__
MT18JSF25672PD(I)Z-1G4__
MT18JSF25672PD(I)Z-1G1__
MT18JSF25672PD(I)Z-1G0__
MT18JSF25672PD(I)Z-80C__
MT18JSF25672PD(I)Z-80B__
Notes: 1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes.
Example: MT18JSF25672PDZ-1G4D1.
PDF: 09005aef8382b0a9 / Source: 09005aef8382b0e2
JSF18C256x72PDZ.fm - Rev. A 2/09 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2009 Micron Technology, Inc. All rights reserved.
2GB (x72, ECC, DR): 240-Pin DDR3 SDRAM RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 4:
Pin Assignments
240-Pin DDR3 RDIMM Front
240-Pin DDR3 RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Vrefdq
Vss
DQ0
DQ1
Vss
DQS0#
DQS0
Vss
DQ2
DQ3
Vss
DQ8
DQ9
Vss
DQS1#
DQS1
Vss
DQ10
DQ11
Vss
DQ16
DQ17
Vss
DQS2#
DQS2
Vss
DQ18
DQ19
Vss
DQ24
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
DQ25
Vss
DQS3#
DQS3
Vss
DQ26
DQ27
Vss
CB0
CB1
Vss
DQS8#
DQS8
Vss
CB2
CB3
Vss
Vtt
Vtt
CKE0
Vdd
BA2
Err_Out#
Vdd
A11
A7
Vdd
A5
A4
Vdd
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
A2
Vdd
NC
NC
Vdd
Vdd
Vrefca
Par_In
Vdd
A10
BA0
Vdd
WE#
CAS#
Vdd
S1#
ODT1
Vdd
NC
Vss
DQ32
DQ33
Vss
DQS4#
DQS4
Vss
DQ34
DQ35
Vss
DQ40
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ41
Vss
DQS5#
DQS5
Vss
DQ42
DQ43
Vss
DQ48
DQ49
Vss
DQS6#
DQS6
Vss
DQ50
DQ51
Vss
DQ56
DQ57
Vss
DQS7#
DQS7
Vss
DQ58
DQ59
Vss
SA0
SCL
SA2
Vtt
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Vss
DQ4
DQ5
Vss
DM0/
TDQS9
NU/
TDQS9#
Vss
DQ6
DQ7
Vss
DQ12
DQ13
Vss
DM1/
TDQS10
NU/
TDQS10#
Vss
DQ14
DQ15
Vss
DQ20
DQ21
Vss
DM2/
TDQS11
NU/
TDQS11#
Vss
DQ22
DQ23
Vss
DQ28
DQ29
151
152
Vss
DM3/
TDQS12
153
NU/
TDQS12#
154
Vss
155 DQ30
156
157
158
159
160
161
DQ31
181
182
183
184
185
186
A1
Vdd
Vdd
CK0
CK0#
Vdd
Vss
DM5/
TDQS14
213
NU/
TDQS14#
214
Vss
215
DQ46
216
DQ47
211
212
Vss
CB4
CB5
Vss
DM8/
TDQS17
162
NU/
TDQS17#
163
Vss
164
CB6
165
CB7
Vss
NC
RESET#
CKE1
Vdd
A15
A14
Vdd
A12
A9
Vdd
A8
A6
Vdd
A3
187 EVENT# 217
188
A0
218
189
Vdd
219
190
BA1
220
191
Vdd
221
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
RAS#
S0#
Vdd
ODT0
A13
Vdd
NC
Vss
DQ36
DQ37
Vss
DM4/
TDQS13
NU/
TDQS13#
Vss
DQ38
DQ39
Vss
DQ44
DQ45
V
SS
DQ52
DQ53
Vss
DM6/
TDQS15
222
NU/
TDQS15#
223
Vss
224
DQ54
225
DQ55
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
226
227
228
229
230
Vss
DQ60
DQ61
Vss
DM7/
TDQS16
231
NU/
TDQS16#
232
Vss
233
DQ62
234
DQ63
Vss
Vddspd
SA1
SDA
Vss
Vtt
235
236
237
238
239
240
PDF: 09005aef8382b0a9 / Source: 09005aef8382b0e2
JSF18C256x72PDZ.fm - Rev. A 2/09 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2009 Micron Technology, Inc. All rights reserved.
2GB (x72, ECC, DR): 240-Pin DDR3 SDRAM RDIMM
Pin Assignments and Descriptions
Table 5:
Symbol
A[15:0]
Pin Descriptions
Type
Input
Description
Address inputs:
Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly”
during CAS commands. The address inputs also provide the op-code during the mode
register command set
.
A[13:0] address the 1Gb DDR3 devices. A[15:14] are needed to
calculate parity on the command/address bus.
Bank address inputs:
BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. BA[2:0] are
used as part of the parity calculation.
Clock:
CK and CK# are differential clock inputs. All control, command, and address
input signals are sampled on the crossing of the positive edge of CK and the negative
edge of CK#.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM.
Input data mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of the DQS. Although the DM pins are input-only, the DM loading is
designed to match that of the DQ and DQS pins. When TDQS is enabled, DM is disabled
and TDQS and TDQS# provide termination resistance, otherwise the TDQS# pins are no
function.
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DRAM. When enabled in normal operation, ODT is
applied only to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be
ignored if disabled via the LOAD MODE command.
Parity input:
Parity bit for the address, RAS#, CAS#, and WE#.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
RESET# is an active LOW CMOS input referenced to Vss. The RESET# input
receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH
≥
0.8 × Vdd and DC
LOW
≤
0.2 × Vdd.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs:
These pins are used to configure the temperature sensor/SPD
EEPROM address range on the I
2
C bus.
Serial clock for temperature sensor/SPD EEPROM:
SCL is used to synchronize
communication to and from the temperature sensor/SPD EEPROM.
Check bits:
Data used for ECC.
Data input/output:
Bidirectional data bus.
Data strobe:
DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data. DQS# is
used only when the differential data strobe mode is enabled via the LOAD MODE
command.
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out
of the temperature sensor/SPD EEPROM on the module on the I
2
C bus.
Parity error output:
Parity error found on the command and address bus.
BA[2:0]
Input
CK0, CK0#
Input
CKE[1:0]
DM[8:0]
(TDQS[17:9],
TDQS#[17:9])
Input
Input
ODT[1:0]
Input
Par_In
RAS#, CAS#, WE#
RESET#
Input
Input
Input
(LVCMOS)
Input
Input
Input
I/O
I/O
I/O
S#[1:0]
SA[2:0]
SCL
CB[7:0]
DQ[63:0]
DQS[8:0],
DQS#[8:0]
SDA
Err_Out#
I/O
Output
(open-drain)
PDF: 09005aef8382b0a9 / Source: 09005aef8382b0e2
JSF18C256x72PDZ.fm - Rev. A 2/09 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2009 Micron Technology, Inc. All rights reserved.
2GB (x72, ECC, DR): 240-Pin DDR3 SDRAM RDIMM
Pin Assignments and Descriptions
Table 5:
Symbol
EVENT#
Vdd
Vddspd
Vrefca
Vrefdq
Vss
Vtt
NC
NU
Pin Descriptions (continued)
Type
Description
Output
Temperature event:
The EVENT# pin is asserted by the temperature sensor when
(open-drain) critical temperature thresholds have been exceeded.
Supply
Power supply:
1.5V ±0.075V. The component Vdd and Vddq are connected to the
module Vdd.
Supply
Temperature sensor/SPD EEPROM power supply:
+3.0V to +3.6V.
Supply
Reference voltage:
Control, command, and address (Vdd/2).
Supply
Reference voltage:
DQ, DM (Vdd/2).
Supply
Ground.
Supply
Termination voltage:
Used for control, command, and address (Vdd/2).
–
No connect:
These pins are not connected on the module.
–
Not used:
These pins are not used in specific module configuration/operations.
The DQ map is provided to enable the designer to locate primary DQ on the DRAM for
the use of read-calibration and write-leveling functions of DDR3. Please see the DRAM
component data sheet for detail on these functions.
Table 6:
Component DQ to Module Pin Map
Component
Number
U1
Component DQ
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Module DQ
2
5
7
0
6
4
3
1
10
13
15
8
14
12
11
9
18
21
23
16
22
20
19
17
Module Pin Number
9
123
129
3
128
122
10
4
18
132
138
12
137
131
19
13
27
141
147
21
146
140
28
22
U2
U3
PDF: 09005aef8382b0a9 / Source: 09005aef8382b0e2
JSF18C256x72PDZ.fm - Rev. A 2/09 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2009 Micron Technology, Inc. All rights reserved.
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