Forward Transconductance (VDS = 15 Vdc, ID = 4.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2.)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(
(VDS = 400 Vdc, ID = 8.0 Adc,
VGS = 10 Vdc)
(VDD = 250 Vdc, ID = 12 Adc,
VGS = 10 Vdc
Vdc,
RG = 9.1
Ω)
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (Note 1.)
(IS = 8.0 Adc, VGS = 0 Vdc)
(IS = 8.0 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 8.0 Adc, VGS = 0 Vdc
8 0 Adc
Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored
Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
1. Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
2. Switching characteristics are independent of operating junction temperature.
LD
—
—
LS
—
7.5
—
3.5
4.5
—
—
nH
trr
ta
tb
QRR
VSD
—
—
—
—
—
—
0.9
0.8
375
155
220
2.75
1.1
—
—
—
—
—
µC
ns
Vdc
—
—
—
—
—
—
—
—
14
17
34
25
25
6.0
8.0
12
30
30
70
50
40
—
—
—
nC
ns
(VDS = 25 Vdc, VGS = 0 Vdc,
Vd
Vd
f = 1.0 MHz)
Ciss
Coss
Crss
—
—
—
1530
380
15
2140
530
30
pF
VGS(th)
2.0
—
RDS(on)
VDS(on)
—
—
gFS
4.0
—
—
7.0
7.2
6.3
—
Mhos
—
2.6
6.5
0.6
4.0
—
0.75
Vdc
mV/°C
Ohm
Vdc
V(BR)DSS
500
—
IDSS
—
—
IGSS(f)
IGSS(r)
—
—
—
—
—
—
10
100
100
100
nAdc
—
560
—
—
Vdc
mV/°C
µAdc
Symbol
Min
Typ
Max
Unit
http://onsemi.com
2
NTB8N50
PACKAGE DIMENSIONS
D2PAK
CASE 418B–03
ISSUE D
C
E
–B–
4
DIM
A
B
C
D
E
G
H
J
K
S
V
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
INCHES
MIN
MAX
0.340
0.380
0.380
0.405
0.160
0.190
0.020
0.035
0.045
0.055
0.100 BSC
0.080
0.110
0.018
0.025
0.090
0.110
0.575
0.625
0.045
0.055
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
8.64
9.65
9.65
10.29
4.06
4.83
0.51
0.89
1.14
1.40
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
14.60
15.88
1.14
1.40
A
1
2
3
S
–T–
SEATING
PLANE
K
G
D
H
3 PL
M
J
0.13 (0.005)
T B
M
STYLE 2:
PIN 1.
2.
3.
4.
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3
NTB8N50
E–FET is a trademark of Semiconductor Components Industries, LLC.
TMOS is a registered trademark of Semiconductor Components Industries, LLC.
ON Semiconductor
and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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