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MJD44H11,
NJVMJD44H11 (NPN),
MJD45H11,
NJVMJD45H11 (PNP)
Complementary Power
Transistors
DPAK For Surface Mount Applications
Designed for general purpose power and switching such as output or
driver stages in applications such as switching regulators, converters,
and power amplifiers.
Features
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SILICON
POWER TRANSISTORS
8 AMPERES
80 VOLTS, 20 WATTS
MARKING
DIAGRAMS
4
1 2
AYWW
J4
xH11G
DPAK
CASE 369C
STYLE 1
4
AYWW
J4
xH11G
2
3
IPAK
CASE 369D
STYLE 1
=
=
=
=
Assembly Location
Year
Work Week
Device Code
x = 4 or 5
= Pb−Free Package
•
Lead Formed for Surface Mount Application in Plastic Sleeves
•
•
•
•
•
•
•
•
•
(No Suffix)
Straight Lead Version in Plastic Sleeves (“−1” Suffix)
Electrically Similar to Popular D44H/D45H Series
Low Collector Emitter Saturation Voltage
−
V
CE(sat)
= 1.0 Volt Max @ 8.0 A
Fast Switching Speeds
Complementary Pairs Simplifies Designs
Epoxy Meets UL 94 V−0 @ 0.125 in
ESD Ratings: Human Body Model, 3B
u
8000 V
Machine Model, C
u
400 V
NJV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These are Pb−Free Packages*
3
1
A
Y
WW
J4xH11
G
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2012
August, 2012
−
Rev. 14
1
Publication Order Number:
MJD44H11/D
MJD44H11, NJVMJD44H11 (NPN), MJD45H11, NJVMJD45H11 (PNP)
MAXIMUM RATINGS
(T
A
= 25_C, common for NPN and PNP, minus sign, “−”, for PNP omitted, unless otherwise noted)
Rating
Collector−Emitter Voltage
Emitter−Base Voltage
Collector Current
−
Continuous
−
Peak
Symbol
V
CEO
V
EB
I
C
P
D
Max
80
5
8
16
20
0.16
1.75
0.014
−55
to +150
Unit
Vdc
Vdc
Adc
W
W/°C
W
W/°C
°C
Total Power Dissipation
@ T
C
= 25°C
Derate above 25°C
Total Power Dissipation (Note 1)
@ T
A
= 25°C
Derate above 25°C
Operating and Storage Junction
Temperature Range
P
D
T
J
, T
stg
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, Junction−to−Case
Thermal Resistance, Junction−to−Ambient (Note 1)
Lead Temperature for Soldering
Symbol
R
qJC
R
qJA
T
L
Max
6.25
71.4
260
Unit
°C/W
°C/W
°C
1. These ratings are applicable when surface mounted on the minimum pad sizes recommended.
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2
MJD44H11, NJVMJD44H11 (NPN), MJD45H11, NJVMJD45H11 (PNP)
ELECTRICAL CHARACTERISTICS
(T
A
= 25_C, common for NPN and PNP, minus sign, “−”, for PNP omitted, unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Collector−Emitter Sustaining Voltage
(I
C
= 30 mA, I
B
= 0)
Collector Cutoff Current
(V
CE
= Rated V
CEO
, V
BE
= 0)
Emitter Cutoff Current
(V
EB
= 5 Vdc)
ON CHARACTERISTICS
Collector−Emitter Saturation Voltage
(I
C
= 8 Adc, I
B
= 0.4 Adc)
Base−Emitter Saturation Voltage
(I
C
= 8 Adc, I
B
= 0.8 Adc)
DC Current Gain
(V
CE
= 1 Vdc, I
C
= 2 Adc)
DC Current Gain
(V
CE
= 1 Vdc, I
C
= 4 Adc)
DYNAMIC CHARACTERISTICS
Collector Capacitance
(V
CB
= 10 Vdc, f
test
= 1 MHz)
MJD44H11, NJVMJD44H11G,/T4G/RLG
MJD45H11, NJVMJD45H11T4G/RLG
C
cb
pF
45
130
MHz
85
90
V
CE(sat)
V
BE(sat)
h
FE
60
40
1
1.5
Vdc
Vdc
−
V
CEO(sus)
I
CES
I
EBO
80
1.0
1.0
Vdc
mA
mA
Symbol
Min
Typ
Max
Unit
Gain Bandwidth Product
(I
C
= 0.5 Adc, V
CE
= 10 Vdc, f = 20 MHz) MJD44H11, NJVMJD44H11G,/T4G/RLG
MJD45H11, NJVMJD45H11T4G/RLG
SWITCHING TIMES
Delay and Rise Times
(I
C
= 5 Adc, I
B1
= 0.5 Adc)
Storage Time
(I
C
= 5 Adc, I
B1
= I
B2
= 0.5 Adc)
Fall Time
(I
C
= 5 Adc, I
B1
= I
B2
= 0.5 Adc
MJD44H11, NJVMJD44H11G,/T4G/RLG
MJD45H11, NJVMJD45H11T4G/RLG
MJD44H11, NJVMJD44H11G,/T4G/RLG
MJD45H11, NJVMJD45H11T4G/RLG
MJD44H11, NJVMJD44H11G,/T4G/RLG
MJD45H11, NJVMJD45H11T4G/RLG
f
T
t
d
+ t
r
ns
300
135
ns
500
500
ns
140
100
t
s
t
f
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3
MJD44H11, NJVMJD44H11 (NPN), MJD45H11, NJVMJD45H11 (PNP)
1
0.7
0.5
0.3
0.2
0.1
0.1
0.07
0.05
0.03
0.02
SINGLE PULSE
0.05
0.02
0.01
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
D = 0.5
0.2
R
qJC(t)
= r(t) R
qJC
R
qJC
= 6.25°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
- T
C
= P
(pk)
q
JC(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
0.01
0.01
0.02 0.03
0.05
0.1
0.2 0.3
0.5
1
2 3
5
t, TIME (ms)
10
20
30
50
100
200 300
500
1k
Figure 1. Thermal Response
20
IC, COLLECTOR CURRENT (AMP)
10
5
3
2
1
0.5
0.3
0.1
THERMAL LIMIT @ T
C
= 25°C
WIRE BOND LIMIT
5 ms
500
ms
dc
100
ms
1 ms
0.05
0.02
1
50
5
7 10
20 30
3
V
CE
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
70 100
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
−
V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 2 is based on T
J(pk)
= 150_C; T
C
is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T
J(pk)
v
150_C. T
J(pk)
may be calculated from the data in
Figure 1. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
Figure 2. Maximum Forward Bias
Safe Operating Area
T
A
T
C
2.5 25
PD, POWER DISSIPATION (WATTS)
2 20
T
C
1.5 15
1 10
T
A
SURFACE
MOUNT
0.5
5
0
0
25
50
75
100
125
150
T, TEMPERATURE (°C)
Figure 3. Power Derating
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