MJD112 (NPN)
MJD117 (PNP)
Preferred Device
Complementary Darlington
Power Transistors
DPAK For Surface Mount Applications
Designed for general purpose power and switching such as output or
driver stages in applications such as switching regulators, converters,
and power amplifiers.
Features
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•
Lead Formed for Surface Mount Applications in Plastic Sleeves
(No Suffix)
•
Straight Lead Version in Plastic Sleeves (“−1” Suffix)
•
Electrically Similar to Popular TIP31 and TIP32 Series
•
Pb−Free Packages are Available
MAXIMUM RATINGS
Rating
Collector−Emitter Voltage
Collector−Base Voltage
Emitter−Base Voltage
Collector Current
Base Current
Total Power Dissipation @ T
C
= 25°C
Derate above 25°C
Total Power Dissipation (Note1)
@ T
A
= 25°C
Derate above 25°C
Operating and Storage Junction
Temperature Range
− Continuous
− Peak
Symbol
V
CEO
V
CB
V
EB
I
C
I
B
P
D
P
D
1.75
0.014
T
J
, T
stg
−65 to +150
Max
100
100
5
2
4
50
20
0.16
Unit
Vdc
Vdc
Vdc
Adc
mAdc
W
W/°C
W
W/°C
°C
1
SILICON
POWER TRANSISTORS
2 AMPERES
100 VOLTS, 20 WATTS
MARKING
DIAGRAMS
4
1 2
3
DPAK
CASE 369C
YWW
J11xG
4
YWW
J11xG
2
3
DPAK−3
CASE 369D
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, Junction−to−Case
Thermal Resistance, Junction−to−Ambient
(Note 1)
Symbol
R
qJC
R
qJA
Max
6.25
71.4
Unit
°C/W
°C/W
Y
WW
x
G
= Year
= Work Week
= 2 or 7
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. These ratings are applicable when surface mounted on the minimum pad
sizes recommended.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
1
January, 2006 − Rev. 6
Publication Order Number:
MJD112/D
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2. Pulse Test: Pulse Width
v
300
ms,
Duty Cycle
v
2%.
*These ratings are applicable when surface mounted on the minimum pad sizes recommended.
DYNAMIC CHARACTERISTICS
ON CHARACTERISTICS
OFF CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
(T
C
= 25_C unless otherwise noted)
Output Capacitance
(V
CB
= 10 Vdc, I
E
= 0, f = 0.1 MHz)
Current−Gain − Bandwidth Product
(I
C
= 0.75 Adc, V
CE
= 10 Vdc, f = 1 MHz)
Base−Emitter On Voltage (I
C
= 2 Adc, V
CE
= 3 Vdc)
Base−Emitter Saturation Voltage (I
C
= 4 Adc, I
B
= 40 mAdc)
Collector−Emitter Saturation Voltage
(I
C
= 2 Adc, I
B
= 8 mAdc)
(I
C
= 4 Adc, I
B
= 40 mAdc)
DC Current Gain
(I
C
= 0.5 Adc, V
CE
= 3 Vdc)
(I
C
= 2 Adc, V
CE
= 3 Vdc)
(I
C
= 4 Adc, V
CE
= 3 Vdc)
Emitter−Cutoff Current (V
BE
= 5 Vdc, I
C
= 0)
Collector−Cutoff Current (V
CB
= 80 Vdc, I
E
= 0)
Emitter Cutoff Current
(V
BE
= 5 Vdc, I
C
= 0)
Collector Cutoff Current
(V
CB
= 100 Vdc, I
E
= 0)
Collector Cutoff Current
(V
CE
= 50 Vdc, I
B
= 0)
Collector−Emitter Sustaining Voltage (Note 2)
(I
C
= 30 mAdc, I
B
= 0)
Characteristic
MJD112 (NPN) MJD117 (PNP)
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MJD117
MJD112
V
CEO(sus)
Symbol
V
CE(sat)
V
BE(sat)
V
BE(on)
I
CBO
I
CBO
I
CEO
I
EBO
I
EBO
C
ob
h
FE
f
T
500
1000
200
Min
100
25
−
−
−
−
−
−
−
−
−
−
−
−
12,000
−
Max
200
100
2.8
10
20
20
−
4
2
3
2
2
−
mAdc
mAdc
mAdc
mAdc
mAdc
MHz
Unit
Vdc
Vdc
Vdc
Vdc
pF
−
2
MJD112 (NPN) MJD117 (PNP)
R
B
& R
C
VARIED TO OBTAIN DESIRED CURRENT LEVELS
D
1
, MUST BE FAST RECOVERY TYPE, e.g.:
1N5825 USED ABOVE I
B
≈
100 mA
MSD6100 USED BELOW I
B
≈
100 mA
TUT
V
2
APPROX
+8 V
0
V
1
APPROX
−12 V
t
r
, t
f
≤
10 ns
DUTY CYCLE = 1%
R
B
51
D
1
+4V
≈
8k
≈
60
V
CC
−30 V
R
C
SCOPE
t, TIME (
μ
s)
4
t
s
2
t
f
t
r
V
CC
= 30 V
I
C
/I
B
= 250
I
B1
= I
B2
T
J
= 25°C
1
0.8
0.6
0.4
PNP
NPN
0.1
25
ms
t
d
@ V
BE(off)
= 0 V
FOR t
d
AND t
r
, D
1
IS DISCONNECTED
AND V
2
= 0
FOR NPN TEST CIRCUIT REVERSE ALL POLARITIES.
0.2
0.04 0.06
0.2
0.4 0.6
1
I
C
, COLLECTOR CURRENT (AMP)
2
4
Figure 1. Switching Times Test Circuit
Figure 2. Switching Times
r(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE (NORMALIZED)
1
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.03
0.02
0.01
0.01
D = 0.5
0.2
0.1
0.05
0.01
SINGLE PULSE
R
qJC(t)
= r(t) R
qJC
R
qJC
= 6.25°C/W
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
− T
C
= P
(pk)
q
JC(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
0.02 0.03
0.05
0.1
0.2 0.3
0.5
1
2 3
5
10
t, TIME OR PULSE WIDTH (ms)
20
30
50
100
200 300
500
1000
Figure 3. Thermal Response
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MJD112 (NPN) MJD117 (PNP)
ACTIVE−REGION SAFE−OPERATING AREA
T
A
T
C
2.5 25
500
ms
1 ms
5 ms
dc
BONDING WIRE LIMITED
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
T
J
= 150°C
CURVES APPLY BELOW RATED V
CEO
2
3
5
7
10
20
30
50
70 100
200
PD, POWER DISSIPATION (WATTS)
100
ms
IC, COLLECTOR CURRENT (AMP)
10
7
5
3
2
1
0.7
0.5
0.3
0.2
0.1
2 20
1.5 15
T
A
SURFACE
MOUNT
T
C
1 10
0.5
5
0
0
25
50
V
CE
, COLLECTOR−EMITTER VOLTAGE (VOLTS)
75
100
T, TEMPERATURE (°C)
125
15
Figure 4. Maximum Rated Forward Biased
Safe Operating Area
Figure 5. Power Derating
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
− V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figures 5 and 6 is based on T
J(pk)
= 150_C; T
C
is variable depending on conditions. Second breakdown
pulse limits are valid for duty cycles to 10% provided
T
J(pk)
< 150_C. T
J(pk)
may be calculated from the data in
Figure 4. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
200
T
C
= 25°C
C, CAPACITANCE (pF)
100
70
50
C
ob
30
C
ib
20
PNP
NPN
10
0.04 0.06 0.1
0.2
0.4 0.6
1
2
4
6
10
20
40
V
R
, REVERSE VOLTAGE (VOLTS)
Figure 6. Capacitance
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MJD112 (NPN) MJD117 (PNP)
TYPICAL ELECTRICAL CHARACTERISTICS
NPN MJD112
6k
T
J
= 125°C
4k
hFE , DC CURRENT GAIN
hFE , DC CURRENT GAIN
3k
2k
25°C
V
CE
= 3 V
4k
3k
2k
25°C
6k
T
C
= 125°C
V
CE
= 3 V
PNP MJD117
1k
800
600
400
300
0.04 0.06
−55
°C
1k
800
600
400
300
0.04 0.06
−55
°C
0.1
0.2
0.4 0.6
1
I
C
, COLLECTOR CURRENT (AMP)
2
4
0.1
0.2
0.4 0.6
1
I
C
, COLLECTOR CURRENT (AMP)
2
4
Figure 7. DC Current Gain
VCE , COLLECTOR−EMITTER VOLTAGE (VOLTS)
VCE , COLLECTOR−EMITTER VOLTAGE (VOLTS)
3.4
T
J
= 125°C
3 I
C
=
0.5 A
2.6
2.2
1.8
1.4
1
0.6
0.1
0.2
0.5
1
2
5
10
20
50
100
3.4
3
2.6
2.2
1.8
1.4
1
0.6
0.1
0.2
0.5
1
2
5
10
20
50
100
I
C
=
0.5 A
1A
2A
4A
T
J
= 125°C
1A
2A
4A
I
B
, BASE CURRENT (mA)
I
B
, BASE CURRENT (mA)
Figure 8. Collector Saturation Region
2.2
T
J
= 25°C
1.8
V, VOLTAGE (VOLTS)
V
BE(sat)
@ I
C
/I
B
= 250
V, VOLTAGE (VOLTS)
1.8
V
BE(sat)
@ I
C
/I
B
= 250
2.2
T
J
= 25°C
1.4
V
BE
@ V
CE
= 3 V
1.4
V
BE
@ V
CE
= 3 V
1
V
CE(sat)
@ I
C
/I
B
= 250
0.6
1
V
CE(sat)
@ I
C
/I
B
= 250
0.6
0.2
0.04 0.06
0.1
0.2
0.4
0.6
1
2
4
0.2
0.04 0.06
0.1
0.2
0.4
0.6
1
2
4
I
C
, COLLECTOR CURRENT (AMP)
I
C
, COLLECTOR CURRENT (AMP)
Figure 9. “On Voltages
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