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MC100EP196B
3.3 V ECL Programmable
Delay Chip With FTUNE
Descriptions
The MC100EP196B is a Programmable Delay Chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides variable
delay of a differential NECL/PECL input transition. It has similar
architecture to the EP195 with the added feature of further tunability in
delay using the FTUNE pin. The FTUNE input takes an analog voltage
from V
CC
to V
EE
to fine tune the output delay from 0 to 60 ps.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 3. The delay
increment of the EP196B has a digitally selectable resolution of about
10 ps and a net range of up to 10.4 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(Pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any subsequent
changes in D[10:0]. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
Table 6 and Figure 4.
The IN/IN inputs can accept LVPECL (SE or Diff), or LVDS level
signals. Because the MC100EP196B is designed using a chain of
multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin
D10 is provided for controlling Pins 14 and 15, CASCADE and
CASCADE, also latched by LEN, in cascading multiple PDCs for
increased programmable range. The cascade logic allows full control of
multiple PDCs. Switching devices from all “1” states on D[0:9] with
SETMAX LOW to all “0” states on D[0:9] with SETMAX HIGH will
increase the delay equivalent to “D0”, the minimum increment.
Select input pins D[10:0] may be threshold controlled by
combinations of interconnects between V
EF
(pin 7) and V
CF
(pin 8) for
receiving LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
levels, leave V
CF
and V
EF
open. For ECL operation, short V
CF
and V
EF
(Pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply
reference to V
CF
and leave open V
EF
pin. The 1.5 V reference voltage at
the V
CF
pin can be accomplished by placing a 2.2 kW resistor between
V
CF
and V
EE
for a 3.3 V power supply.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and
V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking to
0.5 mA. When not used, V
BB
should be left open.
The 100 Series contains temperature compensation.
Features
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MARKING
DIAGRAMS*
LQFP−32
FA SUFFIX
CASE 873A
MC100
EP196B
AWLYYWWG
32
1
1
1
32
QFN32
MN SUFFIX
CASE 488AM
A
L
Y
W
G
MC100
EP196B
ALYWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
•
•
•
•
•
•
Maximum Input Clock Frequency >1.2 GHz Typical
Programmable Range: 0 ns to 10 ns
Delay Range: 2.2 ns to 12.4 ns
10 ps Increments
Linearity
±40
ps max
PECL Mode Operating Range:
V
CC
= 3.0 V to 3.6 V with V
EE
= 0 V
•
NECL Mode Operating Range:
•
•
•
•
•
1
V
CC
= 0 V with V
EE
=
−3.0
V to
−3.6
V
IN/IN Inputs Accept LVPECL, LVNECL, LVDS Levels
A Logic High on the EN Pin Will Force Q to Logic Low
D[10:0] Can Select Either LVPECL, LVCMOS, or
LVTTL Input Levels
V
BB
Output Reference Voltage
These are Pb−Free Devices
Publication Order Number:
MC100EP196B/D
©
Semiconductor Components Industries, LLC, 2008
April, 2008
−
Rev. 1
MC100EP196B
V
EE
D7
D6
D5
D4
D3
D2
26
D1
25
24
23
22
V
EE
D0
V
CC
Q
Q
V
CC
V
CC
FTUNE
21
20
19
18
17
9
10
11
12
13
14
15
16
EN
D1
25
24
23
22
21
32
D8
D9
D10
IN
IN
V
BB
V
EF
V
CF
1
2
3
4
5
6
7
8
31
30
29
28
27
MC100EP196B
SETMAX
SETMIN
CASCADE
D3
27
Warning: All V
CC
and V
EE
pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 32−Lead LQFP
(Top View)
32
31
30
29
28
CASCADE
D2
26
LEN
V
EE
V
CC
V
EE
D6
D5
D4
D7
1
2
3
4
D8
D9
D10
IN
IN
V
BB
V
EF
V
CF
V
EE
D0
V
CC
Q
Q
V
CC
V
CC
FTUNE
MC100EP196B
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
V
EE
Figure 2. 32−Lead QFN
(Top View)
LEN
SETMIN
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2
SETMAX
V
CC
CASCADE
CASCADE
EN
Exposed Pad (EP)
MC100EP196B
Table 1. PIN DESCRIPTION
Pin
23, 25, 26, 27,
29, 30, 31, 32,
1, 2
3
4
5
6
7
8
9, 24, 28
Name
D[0:9]
I/O
LVCMOS, LVTTL,
ECL Input
LVCMOS, LVTTL,
ECL Input
LVPECL, LVDS
LVPECL, LVDS
−
−
−
−
Default State
Low
Description
Single−Ended Parallel Data Inputs [0:9]. Internal 75 kW to V
EE
.
(Note 1)
Single−Ended CASCADE/CASCADE Control Input. Internal 75 kW
to V
EE
. (Note 1)
Noninverted Differential Input. Internal 75 kW to V
EE
.
Inverted Differential Input. Internal 75 kW to V
EE
.
ECL Reference Voltage Output
Reference Voltage for ECL Mode Connection
LVCMOS, ECL, OR LVTTL Input Mode Select
Negative Supply Voltage. All V
EE
Pins must be Externally
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
Positive Supply Voltage. All V
CC
Pins must be externally
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
Single−ended D pins LOAD / HOLD input. Internal 75 kW to V
EE
.
Single−ended Minimum Delay Set Logic Input. Internal 75 kW to
V
EE
. (Note 1)
Single−ended Maximum Delay Set Logic Input. Internal 75 kW to
V
EE
. (Note 1)
Inverted Differential Cascade Output for D[10]. Typically Terminated
with 50
W
to V
TT
= V
CC
−
2 V.
Noninverted Differential Cascade Output. for D[10] Typically
Terminated with 50
W
to V
TT
= V
CC
−
2 V.
Single−ended Output Enable Pin. Internal 75 kW to V
EE
.
Fine Tune Input
Noninverted Differential Output. Typically Terminated with 50
W
to
V
TT
= V
CC
−
2 V.
Inverted Differential Output. Typically Terminated with 50
W
to
V
TT
= V
CC
−
2 V.
D[10]
IN
IN
V
BB
V
EF
V
CF
V
EE
Low
Low
High
−
−
−
−
13, 18, 19, 22
V
CC
−
−
10
11
12
14
15
16
17
21
20
LEN
SETMIN
SETMAX
CASCADE
CASCADE
EN
FTUNE
Q
Q
ECL Input
ECL Input
ECL Input
ECL Output
ECL Output
ECL Input
Analog Input
ECL Output
ECL Output
Low
Low
Low
−
−
Low
−
−
−
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.
2. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation.
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3
MC100EP196B
Table 2. CONTROL PIN
Pin
EN
State
LOW (Note 3)
Function
Input Signal is Propagated to the Output
HIGH
LEN
LOW (Note 3)
HIGH
SETMIN
LOW (Note 3)
HIGH
SETMAX
LOW (Note 3)
HIGH
D10
LOW (Note 3)
HIGH
Output Holds Logic Low State
Transparent or LOAD mode for real time delay values present on D[0:10].
LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10]
are not recognized and do not affect delay.
Output Delay set by D[0:10]
Set Minimum Output Delay
Output Delay set by D[0:10]
Set Maximum Output Delay
CASCADE Output LOW, CASCADE Output HIGH
CASCADE Output LOW, CASCADE Output HIGH
3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected.
Table 3. CONTROL D[0:10] INTERFACE
V
CF
V
CF
V
CF
V
EF
Pin (Note 4)
No Connect
1.5 V
$
100 mV
ECL Mode
LVCMOS Mode
LVTTL Mode (Note 5)
4. Short V
CF
(pin 8) and V
EF
(pin 7).
5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, R
CF
(suggested resistor value
is 2.2 kW
$5%),
between V
CF
and V
EE
pins.
Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE
CONTROL DATA SELECT INPUTS PINS (D [0:10])
POWER SUPPLY
PECL Mode Operating Range
NECL Mode Operating Range
LVCMOS
YES
N/A
LVTTL
YES
N/A
LVPECL
YES
N/A
LVNECL
N/A
YES
Table 5. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
ESD Protection
(R1)
Human Body Model
Machine Model
Charged Device Model
Value
75 kW
> 2 kV
> 100 V
> 2 kV
Pb−Free Pkg
Level 1
Level 2
UL 94 V−0 @ 0.125 in
1237 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 6)
QFN−32
LQFP−32
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
6. For additional information, see Application Note AND8003/D.
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4
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