CAT5221
Dual Digitally Programmable Potentiometer (DPP™) with
64 Taps and 2-wire Interface
FEATURES
Two linear-taper digitally programmable
potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5kΩ, 10kΩ, 50kΩ or
100kΩ
Potentiometer control and memory access via
2-wire interface (I
2
C like)
Low wiper resistance, typically 80Ω
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
20-lead SOIC and TSSOP packages
Industrial temperature range
DESCRIPTION
The CAT5221 is two Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists
of a series of 63 resistive elements connected
between two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DPP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a 2-wire
2
serial bus (I C-like). On power-up, the contents of the
first data register (DR0) for each of the four
potentiometers is automatically loaded into its
respective wiper control register (WCR).
The CAT5221 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
For Ordering Information details, see page 15.
PIN CONFIGURATION
SOIC 20 Lead (W)
TSSOP 20 Lead (Y)
R
W0
R
L0
R
H0
A0
A2
R
W1
R
L1
RH1
SDA
GND
1
2
3
4
20
19
18
17
V
CC
NC
NC
NC
A1
A3
SCL
NC
NC
NC
A0
A1
A2
A3
SCL
SDA
FUNCTIONAL DIAGRAM
R
H0
R
H1
2-WIRE
INTERFACE
WIPER
CONTROL
REGISTERS
R
W0
5
CAT
16
6
5221
15
7
8
9
10
14
13
12
11
R
W1
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R
L0
R
L1
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-2113 Rev. J
CAT5221
PIN DESCRIPTION
Pin (SOIC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
R
W0
R
L0
R
H0
A0
A2
R
W1
R
L1
R
H1
SDA
GND
NC
NC
NC
SCL
A3
A1
NC
NC
NC
V
CC
Function
Wiper Terminal for Potentiometer 0
Low Reference Terminal for Potentiometer 0
High Reference Terminal for Potentiometer 0
Device Address, LSB
Device Address
Wiper Terminal for Potentiometer 1
Low Reference Terminal for Potentiometer 1
High Reference Terminal for Potentiometer 1
Serial Data Input/Output
Ground
No Connect
No Connect
No Connect
Bus Serial Clock
Device Address
Device Address
No Connect
No Connect
No Connect
Supply Voltage
PIN DESCRIPTION
SCL:
Serial Clock
The CAT5221 serial clock input pin is used to clock
all data transfers into or out of the device.
SDA:
Serial Data
The CAT5221 bidirectional serial data pin is used to
transfer data into and out of the device. The SDA pin
is an open drain output and can be wire-Or'd with
the other open drain or open collector outputs.
A0, A1, A2, A3:
Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A match
in the slave address must be made with the address
input in order to initiate communication with the
CAT5221.
R
H
, R
L
:
Resistor End Points
The two sets of R
H
and R
L
pins are equivalent to the
terminal connections on a mechanical potentiometer.
R
W
:
Wiper
The two R
W
pins are equivalent to the wiper terminal
of a mechanical potentiometer.
DEVICE OPERATION
The CAT5221 is two resistor arrays integrated with 2-
wire serial interface logic, two 6-bit wiper control
registers and eight 6-bit, non-volatile memory data
registers. Each resistor array contains 63 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (R
H
and R
L
). R
H
and R
L
are symmetrical and may be interchanged. The tap
positions between and at the ends of the series resis–
tors are connected to the output wiper terminals (R
W
) by
a CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a
time and is determined by the value of the wiper control
register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via
the 2-wire bus. Additional instructions allow data to be
transferred between the wiper control registers and
each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate
in an "increment/decrement" mode.
Doc. No. MD-2113 Rev. J
2
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5221
ABSOLUTE MAXIMUM RATINGS
(1)
Parameter
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to V
SS(2)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10s)
Wiper Current
RECOMMENDED OPERATING CONDITIONS
V
cc
= +2.5V to +6V
Parameter
Operating Ambient Temperature (Industrial)
Ratings
-40 to +85
Units
°C
Ratings
-55 to +125
-65 to +150
-2.0 to +V
CC
+2.0
-2.0 to +7.0
1.0
300
±12
Units
°C
°C
V
V
W
°C
mA
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
R
POT
R
POT
R
POT
R
POT
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance (-10)
Potentiometer Resistance (-2.5)
Potentiometer Resistance Tolerance
R
POT
Matching
Power Rating
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Noise
Resolution
Absolute Linearity
(5)
Relative Linearity
(6)
Temperature Coefficient of R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
Test Conditions
Min
Typ
100
50
10
2.5
±20
1
50
±6
300
150
V
CC
Max
Units
kΩ
kΩ
kΩ
kΩ
%
%
mW
mA
Ω
Ω
nV/√Hz
±1
±0.2
±300
20
10/10/25
0.4
%
LSB
(7)
LSB
(7)
ppm/°C
ppm/°C
pF
MHz
25°C, each pot
I
W
= +3mA @ V
CC
=3V
I
W
= +3mA @ V
CC
= 5V
V
SS
= 0V
(4)
R
W(n)(actual)
- R
(n)(expected)
R
W(n+1)
- [R
W(n)+LSB
]
(8)
(4)
(4)
(4)
R
POT
= 50kΩ
(8)
I
W
R
W
R
W
V
TERM
V
N
80
GND
TBD
1.6
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20ns.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+ 1V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(7) LSB = R
TOT
/ 63 or (R
H
- R
L
) / 63, single pot
(8) n = 0, 1, 2, ..., 63
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-2113 Rev. J
CAT5221
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Power Supply Current
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3.0V)
I
OL
= 3 mA
Test Conditions
f
SCL
= 400kHz
V
IN
= GND or V
CC
; SDA Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
-1
V
CC
x 0.7
Min
Typ
Max
1
1
10
10
V
CC
x 0.3
V
CC
+ 1.0
0.4
Units
mA
µA
µA
µA
V
V
V
CAPACITANCE
T
A
= 25°C, f = 1.0MHz, V
CC
= 5V
Symbol
C
I/O(1)
C
IN(1)
Parameter
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL)
Test Conditions
V
I/O
= 0V
V
IN
= 0V
Min
Typ
Max
8
6
Units
pF
pF
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
f
SCL
T
I
(1)
Parameter
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (For a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Min
Typ
Max
400
50
0.9
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
1.2
0.6
1.2
0.6
0.6
0
100
0.3
300
0.6
50
µs
ns
µs
ns
POWER UP TIMING
(1)
Over recommended operating conditions unless otherwise stated.
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-2113 Rev. J
4
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5221
WRITE CYCLE LIMITS
Over recommended operating conditions unless otherwise stated.
Symbol
t
WR
Parameter
Write Cycle Time
Min
Typ
Max
5
Units
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the
device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
NEND
(1)
TDR
(1)
VZAP
(1)
ILTH
(1)(2)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Typ
Max
Units
Cycles/Byte
Years
Volts
mA
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
SDA IN
tAA
SDA OUT
tDH
tBUF
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHIGH
tLOW
tR
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
STOP BIT
5
Doc. No. MD-2113 Rev. J
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