The PE4122 is a high linearity, passive MOSFET Quad
Mixer for PCS & 3G Base Station Receivers, exhibiting
high dynamic range performance over an LO drive range
of +14 dBm to +20 dBm. This mixer integrates passive
matching networks to provide single-ended interfaces for
the RF and LO ports, eliminating the need for external
RF baluns or matching networks. The PE4122 is
optimized for frequency down conversion using low-side
LO injection for PCS & 3G Base Station applications.
The PE4122 is manufactured in Peregrine’s patented
Ultra-Thin Silicon (UTSi®) CMOS process, offering the
performance of GaAs with the economy and integration
of conventional CMOS.
Figure 1. Functional Schematic Diagram
LO
High Linearity MOSFET Quad
Mixer For PCS & 3G BTS
Features
•
Integrated, Single Ended RF &
LO Interfaces
•
High linearity: IIP3 >+ 30 dBm,
1.8
−
2.0 GHz (+17 dBm LO)
•
Low-conversion loss: 7.6 dB
(+17 dBm LO)
•
High Isolation: Typical LO-IF at
38 dB / LO-RF at 34 dB
•
Designed for Low-Side LO
Injection
Figure 2. Package Drawings
3.10
2.90
RF
PE4122
IF
8-Lead TSSOP
6.50
6.25
Table 1. Electrical Specifications @ +25 °C
(Z
S
= Z
L
= 50
Ω)
Parameter
Frequency Range:
LO
RF
IF
Conversion Loss
Isolation:
LO-RF
LO-IF
Input IP3
1.8 GHz
1.9 GHz
2.0 GHZ
Input 1 dB Compression
24
26
27
30
27
Minimum
1540
1800
--
Typical
--
--
260*
7.6
34
38
30
33
30
20
Maximum
1740
2000
--
8.3
Units
MHz
MHz
MHz
dB
dB
dB
dBm
dBm
dBm
dBm
*An IF frequency of 260 MHz is a nominal frequency. The IF frequency can be specified by the user as long as the RF and LO frequencies are within the specified maximum
and minimum.
Test conditions unless otherwise noted: LO input drive = 17 dBm, RF input drive = 0 dBm
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2001
Page 1 of 10
PE4122-260
Preliminary Specification
Figure 3. Pin Configuration
1
LO
GND
8
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the same
precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.
2
GND
IF1
7
3
RF
IF2
6
4
GND
PE4122
GND
5
Table 2. Pin Descriptions
Pin
No.
1
2
Pin
Name
LO
GND
LO Input
Description
Ground connection for Mixer. Traces
should be physically short and connect
immediately to ground plane for best
performance.
RF Input
Ground.
Ground.
IF differential output
IF differential output
Ground.
3
4
5
6
7
8
RF
GND
GND
IF1
IF2
GND
Table 3. Absolute Maximum Ratings
Symbol
T
ST
T
OP
P
LO
P
RF
VESD
Parameter/Conditions
Storage temperature
range
Operating temperature
range
LO input power
RF input power
ESD Sensitive Device
Min
-65
-40
Max
150
85
20
20
100
Units
°C
°C
dBm
dBm
V
Copyright
Peregrine Semiconductor Corp. 2001
File No. 70/0041~02B
|
UTSi
CMOS RFIC SOLUTIONS
Page 2 of 10
PE4122-260
Preliminary Specification
Evaluation Board
Figure 4 is the Schematic for the evaluation test board while Figure 5 shows the board layout. The PE4122 has
on-chip passive matching networks for the RF and LO inputs, eliminating the need for additional passive
components or RF baluns on the RF and LO inputs. The RF input is tuned for an input of 1.8 GHz to 2.0 GHz.
The LO input is designed for low-side injection over a frequency range of 1.54 GHz to 1.74 GHz. Figure 6
shows the test circuit used for a 2-tone, third order intercept measurement.
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