电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

MC74HC175ADTEL

产品描述IC,FLIP-FLOP,QUAD,D TYPE,HC-CMOS,TSSOP,16PIN,PLASTIC
产品类别逻辑    逻辑   
文件大小191KB,共8页
制造商ON Semiconductor(安森美)
官网地址http://www.onsemi.cn
下载文档 详细参数 全文预览

MC74HC175ADTEL概述

IC,FLIP-FLOP,QUAD,D TYPE,HC-CMOS,TSSOP,16PIN,PLASTIC

MC74HC175ADTEL规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称ON Semiconductor(安森美)
包装说明TSSOP, TSSOP16,.25
Reach Compliance Codenot_compliant
JESD-30 代码R-PDSO-G16
JESD-609代码e0
负载电容(CL)50 pF
逻辑集成电路类型D FLIP-FLOP
最大频率@ Nom-Sup6000000 Hz
最大I(ol)0.0024 A
功能数量4
端子数量16
最高工作温度125 °C
最低工作温度-55 °C
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP16,.25
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法TAPE AND REEL
电源2/6 V
认证状态Not Qualified
表面贴装YES
技术CMOS
温度等级MILITARY
端子面层Tin/Lead (Sn/Pb)
端子形式GULL WING
端子节距0.635 mm
端子位置DUAL
触发器类型POSITIVE EDGE

文档预览

下载PDF文档
MC74HC175A
Quad D Flip-Flop with
Common Clock and Reset
High–Performance Silicon–Gate CMOS
The MC74HC175A is identical in pinout to the LS175. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of four D flip–flops with common Reset and
Clock inputs, and separate D inputs. Reset (active–low) is
asynchronous and occurs when a low level is applied to the Reset
input. Information at a D input is transferred to the corresponding Q
output on the next positive going edge of the Clock input.
http://onsemi.com
MARKING
DIAGRAMS
16
16
1
PDIP–16
N SUFFIX
CASE 648
MC74HC175AN
AWLYYWW
1
16
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity 166 FETs or 41.5 Equivalent Gates
LOGIC DIAGRAM
CLOCK
9
2
3
7
6
10
11
15
14
1
PIN 16 = VCC
PIN 8 = GND
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
16
1
SO–16
D SUFFIX
CASE 751B
1
HC175A
AWLYWW
16
TSSOP–16
DT SUFFIX
CASE 948F
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
HC
175A
ALYW
16
1
D0
DATA
INPUTS
D1
4
5
D2 12
D3 13
RESET
INVERTING
AND
NONINVERTING
OUTPUTS
PIN ASSIGNMENT
RESET
Q0
Q0
D0
D1
Q1
Q1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
Q3
Q3
D3
D2
Q2
Q2
CLOCK
FUNCTION TABLE
Inputs
Reset
L
H
H
H
Clock
X
D
X
H
L
X
Outputs
Q
Q
L
H
H
L
L
H
No Change
GND
L
ORDERING INFORMATION
Device
MC74HC175AN
MC74HC175AD
MC74HC175ADR2
MC74HC175ADT
MC74HC175ADTR2
Package
PDIP–16
SOIC–16
SOIC–16
TSSOP–16
TSSOP–16
Shipping
2000 / Box
48 / Rail
2500 / Reel
96 / Rail
2500 / Reel
©
Semiconductor Components Industries, LLC, 1999
1
March, 2000 – Rev. 2
Publication Order Number:
MC74HC175A/D

技术资料推荐更多

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 1846  2864  1668  2026  769  27  42  28  11  10 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved