128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
Features
DDR SDRAM Small-Outline DIMM
MT5VDDT1672H – 128MB
MT5VDDT3272H – 256MB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• 200-pin, small-outline dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC-2100, PC-2700,
or PC-3200
• 128MB
2
(16 Meg x 72) and 256MB (32 Meg x 72)
• Supports ECC error detection and correction
• V
DD
= V
DD
Q = +2.5V
• V
DDSPD
= +2.3V to +3.6V
• JEDEC-standard 2.5V I/O (SSTL_2-compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data (source-synchronous data
capture)
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent operation
• Selectable burst lengths (BL): 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes: 7.8125µs
maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable READ CAS latency for maximum
compatibility
• Gold edge contacts
Figure 1:
200-Pin SODIMM (MO-224 R/C C)
Module height: 31.75mm (1.25in)
Options
Marking
• Operating temperature
1
– Commercial (0°C
≤
T
A
≤
+70°C)
None
– Industrial (–40°C
≤
T
A
≤
+85°C)
I
• Package
– 200-pin SODIMM (standard)
2
G
– 200-pin SODIMM (Pb-free)
Y
• Memory clock, frequency, CAS latency
– 5ns (200 MHz), 400 MT/s, CL = 3
-40B
3
– 6ns (167 MHz), 333 MT/s, CL = 2.5
-335
– 7.5ns (133 MHz), 266 MT/s, CL = 2
-262
– 7.5ns (133 MHz), 266 MT/s, CL = 2
-26A
– 7.5ns (133 MHz), 266 MT/s, CL = 2.5
-265
• PCB height
– 31.75mm (1.25in)
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. Consult factory for product availability.
3. -40B only available for 256MB modules.
Table 1:
Speed
Grade
-40B
-335
-262
-26A
-265
Key Timing Parameters
Data Rate (MT/s)
Industry Nomenclature
PC-3200
PC-2700
PC-2100
PC-2100
PC-2100
CL = 3
400
–
–
–
–
CL = 2.5
333
333
266
266
266
CL = 2
266
266
266
266
200
t
RCD
(ns)
15
15
15
20
20
RP
(ns)
15
15
15
20
20
t
RC
(ns)
55
60
60
65
65
t
PDF: 09005aef80a8e793/Source: 09005aef80a8e767
dd5c16_32x72h.fm - Rev. F 2/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
Features
Table 2:
Addressing
128MB
256MB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (32 Meg x 16)
1K (A0–A9)
1 (SO#)
Refresh count
Row addressing
Device bank addressing
Device configuration
Column addressing
Module rank addressing
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (16 Meg x 16)
512 (A0–A8)
1 (SO#)
Table 3:
Part Numbers and Timing Parameters
–
128MB
Base device: MT46V16M16
1
, 256Mb DDR SDRAM
Part Number
2
MT5VDDT1672H(I)G-335__
MT5VDDT1672H(I)Y-335__
MT5VDDT1672H(I)G-262__
MT5VDDT1672H(I)Y-262__
MT5VDDT1672H(I)G-26A__
MT5VDDT1672H(I)Y-26A__
MT5VDDT1672H(I)G-265__
MT5VDDT1672H(I)Y-265__
Module
Density
128MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
Configuration
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
Module
Bandwidth
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
Memory Clock/
Data Rate
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
Latency
(CL-
t
RCD-
t
RP)
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
Table 4:
Part Numbers and Timing Parameters
–
256MB
Base device: MT46V32M16
1
, 512Mb DDR SDRAM
Part
Number
2
Module
Density
256MB
256MB
256MB
256MB
Configuration
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
Module
Bandwidth
3.2 GB/s
3.2 GB/s
2.7 GB/s
2.7 GB/s
Memory Clock/
Data Rate
5ns/400 MT/s
5ns/400 MT/s
6ns/333 MT/s
6ns/333 MT/s
Latency
(CL-
t
RCD-
t
RP)
3-3-3
3-3-3
2.5-3-3
2.5-3-3
MT5VDDT3272H(I)G-40B__
MT5VDDT3272H(I)Y-40B__
MT5VDDT3272H(I)G-335__
MT5VDDT3272H(I)Y-335__
Notes:
1. Data sheets for the base device parts can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT5VDDT1672HG-335F3.
PDF: 09005aef80a8e793/Source: 09005aef80a8e767
dd5c16_32x72h.fm - Rev. F 2/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 5:
Pin Assignments
200-Pin SODIMM Front
Pin Symbol Pin Symbol
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
V
REF
V
SS
DQ0
DQ1
V
DD
DQS0
DQ2
V
SS
DQ3
DQ8
V
DD
DQ9
DQS1
V
SS
DQ10
DQ11
V
DD
CK0
CK0#
V
SS
DQ16
DQ17
V
DD
DQS2
DQ18
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
V
SS
DQ19
DQ24
V
DD
DQ25
DQS3
V
SS
DQ26
DQ27
V
DD
CB0
CB1
V
SS
DQS8
CB2
V
DD
CB3
NC
V
SS
CK2
CK2#
V
DD
NC
NC
A12
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
200-Pin SODIMM Back
Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
A9
V
SS
A7
A5
A3
A1
V
DD
A10
BA0
WE#
S0#
NC
V
SS
DQ32
DQ33
V
DD
DQS4
DQ34
V
SS
DQ35
DQ40
V
DD
DQ41
DQS5
V
SS
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DQ42
DQ43
V
DD
V
DD
V
SS
V
SS
DQ48
DQ49
V
DD
DQS6
DQ50
V
SS
DQ51
DQ56
V
DD
DQ57
DQS7
V
SS
DQ58
DQ59
V
DD
SDA
SCL
V
DDSPD
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
V
REF
V
SS
DQ4
DQ5
V
DD
DM0
DQ6
V
SS
DQ7
DQ12
V
DD
DQ13
DM1
V
SS
DQ14
DQ15
V
DD
V
DD
V
SS
V
SS
DQ20
DQ21
V
DD
DM2
DQ22
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
V
SS
DQ23
DQ28
V
DD
DQ29
DM3
V
SS
DQ30
DQ31
V
DD
CB4
CB5
V
SS
DM8
CB6
V
DD
CB7
NC
V
SS
V
SS
V
DD
V
DD
CKE0
NC
A11
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
A8
V
SS
A6
A4
A2
A0
V
DD
BA1
RAS#
CAS#
NC
NC
V
SS
DQ36
DQ37
V
DD
DM4
DQ38
V
SS
DQ39
DQ44
V
DD
DQ45
DM5
V
SS
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ46
DQ47
V
DD
CK1#
CK1
V
SS
DQ52
DQ53
V
DD
DM6
DQ54
V
SS
DQ55
DQ60
V
DD
DQ61
DM7
V
SS
DQ62
DQ63
V
DD
SA0
SA1
SA2
NC
PDF: 09005aef80a8e793/Source: 09005aef80a8e767
dd5c16_32x72h.fm - Rev. F 2/07 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
Pin Assignments and Descriptions
Table 6:
Pin Descriptions
Type
Input
Input
Description
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Clocks:
CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and negative edge
of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#.
Clock enable:
CKE HIGH activates and CKE LOW deactivates the internal clock,
input buffers and output drivers.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when S# is registered HIGH. S# is
considered part of the command code.
Bank address:
BA0 and BA1 define the device bank to which an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
Address inputs:
Provide the row address for ACTIVE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective device bank. A10 sampled
during a PRECHARGE command determines whether the PRECHARGE applies to
one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks
(A10 HIGH). The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode register (mode register
or extended mode register) is loaded during the LOAD MODE REGISTER
command.
Data mask:
DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM
is sampled on both edges of DQS. Although DM pins are input-only, the DM
loading is designed to match that of DQ and DQS pins.
Serial presence-detect data:
SDA is a bidirectional pin used to transfer
addresses and data into and out of the presence-detect portion of the module.
Serial clock for presence-detect:
SCL is used to synchronize the presence-
detect data transfer to and from the module.
Presence-detect address inputs:
These pins are used to configure the
presence-detect device.
Data strobe:
Output with READ data, input with WRITE data. DQS is edge-
aligned with READ data, centered in WRITE data. Used to capture data.
Check bits.
Data input/output:
Data bus.
SSTL_2 reference voltage.
Power supply:
+2.5V ±0.2V. (-40B speed grade requires 2.6V ±0.1V)
Ground.
Serial EEPROM positive power supply:
+2.3V to +3.6V.
No connect:
These pins should be left unconnected.
Symbol
WE#, CAS#,
RAS#
CK0, CK0#, CK1,
CK1#, CK2, CK2#
CKE0
S0#
Input
Input
BA0, BA1
A0–A12
Input
Input
DM0–DM8
Input
SDA
SCL
SA0–SA2
DQS0–DQS8
CB0–CB7
DQ0–DQ63
V
REF
V
DD
V
SS
V
DDSPD
NC
Input/
Output
Input
Input
Input/
Output
Input/
Output
Input/
Output
Supply
Supply
Supply
Supply
–
PDF: 09005aef80a8e793/Source: 09005aef80a8e767
dd5c16_32x72h.fm - Rev. F 2/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
Functional Block Diagram
Functional Block Diagram
Figure 2:
Functional Block Diagram
S0#
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
UDQS
UDM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS#
DQS8
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
U1
DQS5
DM5
U4
UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LDQS
CS#
U6
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
V
DD
V
DD
NC
NC
NC
NC
NC
NC
NC
NC
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS2
DM2
CS#
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LDQS
LDM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS#
U2
DQS7
DM7
U5
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
BA0–BA1
A0–A12 (128MB, 256MB)
RAS#
CAS#
WE#
CKE0
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
SCL
WP
V
SS
SPD EEPROM
U3
A0
A1
A2
V
DDSPD
SDA
V
DD
V
REF
V
SS
SPD EEPROM
DDR SDRAM
DDR SDRAM
DDR SDRAM
SA0 SA1 SA2
CK0
CK0#
DDR SDRAM U1, U2
CK1
CK1#
DDR SDRAM U4, U5
CK2
CK2#
DDR SDRAM U6
PDF: 09005aef80a8e793/Source: 09005aef80a8e767
dd5c16_32x72h.fm - Rev. F 2/07 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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