64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Features
DDR SDRAM UDIMM
MT5VDDT872A – 64MB
1
MT5VDDT1672A – 128MB
2
MT5VDDT3272A – 256MB
2
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• 184-pin, unbuffered dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC2100, PC2700, or PC3200
• 64MB (8 Meg x 72), 128MB (16 Meg x 72), and
256MB (32 Meg x 72)
• Supports ECC error detection and correction
• V
DD
= V
DD
Q = +2.5V
(-40B: V
DD
= V
DD
Q = +2.6V)
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2-compatible)
• Internal, pipelined double data rate (DDR)
2n-prefetch architecture
• Bidirectional data strobe (DQS) transmitted/
received with data—that is, source-synchronous
data capture
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent
operation
• Single rank
• Selectable burst lengths (BL): 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes:
64MB = 15.625µs and 128MB, 256MB = 7.8125µs
maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum
compatibility
• Gold edge contacts
Table 1:
Speed
Grade
-40B
-335
-262
-26A
-265
Figure 1:
184-Pin UDIMM (MO-206 R/C C)
PCB height: 31.75mm (1.25in)
Options
• Operating temperature
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
• Package
–
184-pin DIMM (standard)
–
184-pin DIMM (Pb-free)
• Memory clock, speed, CAS latency
–
5.0ns (200 MHz), 400 MT/s, CL = 3.0
–
6.0ns (167 MHz), 333 MT/s, CL = 2.5
–
7.5ns (133 MHz), 266 MT/s, CL = 2.0
–
7.5ns (133 MHz), 266 MT/s, CL = 2.0
–
7.5ns (133 MHz), 266 MT/s, CL = 2.5
3
Marking
None
I
G
Y
-40B
-335
-262
-26A
-265
Notes: 1. End of life.
2. Not recommended for new designs.
3. Contact Micron for industrial temperature
module offerings.
Key Timing Parameters
Industry
Nomenclature
PC3200
PC2700
PC2100
PC2100
PC2100
Notes:
Data Rate (MT/s)
CL = 3
400
–
–
–
–
CL = 2.5
333
333
266
266
266
CL = 2
266
266
266
266
200
t
RCD
t
RP
t
RC
(ns)
15
18
15
20
20
(ns)
15
18
15
20
20
(ns)
55
60
60
65
65
Notes
1
1. The values of
t
RCD and
t
RP for -335 modules show 18ns to align with industry specifications;
actual DDR SDRAM device specifications are 15ns.
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Features
Table 2:
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
Addressing
64MB
4K
4K (A0–A11)
4 (BA0, BA1)
128Mb (8 Meg x 16)
512 (A0–A8)
1 (S0#)
128MB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (16 Meg x 16)
512 (A0–A8)
1 (S0#)
256MB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (32 Meg x 16)
1K (A0–A9)
1 (S0#)
Table 3:
Part Numbers and Timing Parameters – 64MB Modules
Base device: MT46V8M16,
1
128Mb DDR SDRAM
Module
Density
64MB
64MB
64MB
64MB
Module
Bandwidth
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
Memory Clock/
Data Rate
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
2.5-3-3
2-2-2
2-3-3
2.5-3-3
Part Number
2
Configuration
8 Meg x 72
8 Meg x 72
8 Meg x 72
8 Meg x 72
MT5VDDT872AG-335__
MT5VDDT872AG-262__
MT5VDDT872AG-26A__
MT5VDDT872AG-265__
Table 4:
Part Numbers and Timing Parameters – 128MB Modules
Base device: MT46V16M16,
1
256Mb DDR SDRAM
Module
Density
128MB
128MB
128MB
128MB
128MB
128MB
Module
Bandwidth
3.2 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
Memory Clock/
Data Rate
5.0ns/400 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
3-3-3
2.5-3-3
2.5-3-3
2-2-2
2-3-3
2.5-3-3
Part Number
2
MT5VDDT1672AG-40B__
MT5VDDT1672AG-335__
MT5VDDT1672AY-335__
MT5VDDT1672AG-262__
MT5VDDT1672AG-26A__
MT5VDDT1672AG-265__
Configuration
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
Table 5:
Part Numbers and Timing Parameters – 256MB Modules
Base device: MT46V32M16,
1
512Mb DDR SDRAM
Module
Density
256MB
256MB
256MB
256MB
256MB
Module
Bandwidth
3.2 GB/s
3.2 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
Memory Clock/
Data Rate
5.0ns/400 MT/s
5.0ns/400 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
3-3-3
3-3-3
2.5-3-3
2.5-3-3
2.5-3-3
Part Number
2
MT5VDDT3272AG-40B__
MT5VDDT3272AY-40B__
MT5VDDT3272AG-335__
MT5VDDT3272AY-335__
MT5VDDT3272AG-265__
Notes:
Configuration
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes. Example: MT5VDDT1672AY-335F3.
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 6:
Pin Assignments
184-Pin DDR UDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
NC
V
SS
DQ8
DQ9
DQS1
V
DD
Q
CK1
CK1#
V
SS
DQ10
DQ11
CKE0
V
DD
Q
DQ16
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DD
Q
DQ19
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
CB0
CB1
V
DD
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
DQS8
A0
CB2
V
SS
CB3
BA1
DQ32
V
DD
Q
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
V
DD
Q
WE#
DQ41
CAS#
V
SS
DQS5
DQ42
DQ43
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
V
DD
NC
DQ48
DQ49
V
SS
CK2#
CK2
V
DD
Q
DQS6
DQ50
DQ51
V
SS
NC
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
V
SS
DQ4
DQ5
V
DD
Q
DM0/
DQS9
DQ6
DQ7
V
SS
NC
NC
NC
V
DD
Q
DQ12
DQ13
DM1/
DQS10
V
DD
DQ14
DQ15
NC
V
DD
Q
NC
DQ20
A12
184-Pin DDR UDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
V
SS
DQ21
A11
DM2/
DQS11
V
DD
DQ22
A8
DQ23
V
SS
A6
DQ28
DQ29
V
DD
Q
DM3/
DQS12
A3
DQ30
V
SS
DQ31
CB4
CB5
V
DD
Q
CK0
CK0#
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
V
SS
DM8/
DQS17
A10
CB6
V
DD
Q
CB7
V
SS
DQ36
DQ37
V
DD
DM4/
DQS13
DQ38
DQ39
V
SS
DQ44
RAS#
DQ45
V
DD
Q
S0#
NC
DM5/
DQS14
V
SS
DQ46
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
DQ47
NC
V
DD
Q
DQ52
DQ53
NC
V
DD
DM6/
DQS15
DQ54
DQ55
V
DD
Q
NC
DQ60
DQ61
V
SS
DM7/
DQS16
DQ62
DQ63
V
DD
Q
SA0
SA1
SA2
V
DDSPD
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Pin Assignments and Descriptions
Table 7:
Pin Descriptions
Symbol
A0–A12
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD MODE
REGISTER command. A0–A11 (64MB) and A0–A12 (128MB, 256MB).
Bank address:
BA0 and BA1 define to which device bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
Clock:
CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and the negative
edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK
and CK#.
Clock enable:
CKE (registered HIGH) activates and CKE (registered LOW)
deactivates the internal clock, input buffers, and output drivers.
Data input mask:
DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH, along with that input data, during a write
access. DM is sampled on both edges of DQS. Although DM pins are input-only,
the DM loading is designed to match that of DQ and DQS pins.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Chip selects:
S# (registered LOW) enables and (registered HIGH) disables the
command decoder.
Presence-detect address inputs:
These pins are used to configure the
presence-detect device.
Serial clock for presence-detect:
SCL is used to synchronize the presence-
detect data transfer to and from the module.
Check bits.
Data input/output:
Data bus.
Data strobe:
Output with read data, input with write data. DQS is edge-
aligned with read data, center-aligned with write data. Used to capture data.
Serial presence-detect data:
SDA is a bidirectional pin used to transfer
addresses and data into and out of the presence-detect portion of the module.
Power supply:
+2.5V ±0.2V (-40B: +2.6V ±0.1V).
Serial EEPROM positive power supply:
+2.3V to +3.6V.
SSTL_2 reference voltage (V
DD
/2).
Ground.
No connect:
These pins are not connected on the module.
BA0, BA1
CK0, CK0#,
CK1, CK1#,
CK2, CK2#
CKE1
DM0–DM8
(DQS9–DQS17)
Input
Input
Input
Input
RAS#, CAS#, WE#
S0#
SA0–SA2
SCL
CB0–CB7
DQ0–DQ63
DQS0–DQS7
SDA
V
DD
/V
DD
Q
V
DDSPD
V
REF
V
SS
NC
Input
Input
Input
Input
I/O
I/O
I/O
I/O
Supply
Supply
Supply
Supply
–
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2:
Functional Block Diagram
S0#
S0#
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3/DQS12
UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S0#
DQS4
DM4/DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5/DQS14
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S0#
S0#
DQS8
DM8/DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
V
SS
V
DD
NC
NC
NC
NC
NC
NC
NC
NC
UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S0#
U1
U4
U3
DQS6
DM6/DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7/DQS16
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U2
UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U5
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
BA0–BA1
A0–A11/A12
RAS#
CAS#
WE#
CKE0
CK0
CK0#
CK1
CK1#
CK2
CK2#
DDR SDRAM
A0–A11/A12 DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM U3
DDR SDRAM U1, U2
DDR SDRAM U4, U5
U6
SCL
SPD EEPROM
WP
A0 A1 A2
SDA
V
SS
SA0 SA1 SA2
V
DDSPD
V
DD
/V
DD
Q
V
REF
V
SS
SPD EEPROM
DDR SDRAM
DDR SDRAM
DDR SDRAM
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
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