4, 8 MEG x 64
DRAM SODIMMs
SMALL-OUTLINE
DRAM MODULE
FEATURES
• JEDEC pinout in a 144-pin, small-outline, dual in-line
memory module (SODIMM)
• 32MB (4 Meg x 64) and 64MB (8 Meg x 64)
• High-performance CMOS silicon-gate process
• Single +3.3V
±0.3V
power supply
• All inputs, outputs and clocks are TTL-compatible
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh
distributed across 64ms
• FAST PAGE MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• Optional Self Refresh Mode (S)
• Serial presence-detect (SPD)
MT4LDT464H (X)(S), MT8LDT864H (X)(S)
For the latest full-length data sheet, please refer to the
Micron Web site:
www.micron.com/mti/msp/html/
datasheet.html
PIN ASSIGNMENT (Front View)
144-Pin Small-Outline DIMM
(I-1; 32MB)
(I-2; 64MB)
OPTIONS
• Package
144-pin SODIMM (gold)
• Timing
50ns access
60ns access
• Access Cycles
FAST PAGE MODE
EDO PAGE MODE
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
*Contact factory for availability
MARKING
G
-5
-6
None
X
None
S*
KEY TIMING PARAMETERS
FPM Operating Mode
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
90ns
110ns
50ns
60ns
30ns
35ns
25ns
30ns
13ns
15ns
30ns
40ns
EDO Operating Mode
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
FRONT
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
V
SS
CAS0#
CAS1#
V
DD
A0
A1
A2
V
SS
DQ8
DQ9
DQ10
DQ11
V
DD
DQ12
DQ13
DQ14
DQ15
V
SS
RSVD
RSVD
RFU
V
DD
RFU
WE#
RAS0#
NC
PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
BACK
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
V
SS
CAS4#
CAS5#
V
DD
A3
A4
A5
V
SS
DQ40
DQ41
DQ42
DQ43
V
DD
DQ44
DQ45
DQ46
DQ47
V
SS
RSVD
RSVD
RFU
V
DD
RFU
RFU
NC
NC
PIN
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
FRONT
OE#
V
SS
RSVD
RSVD
V
DD
DQ16
DQ17
DQ18
DQ19
V
SS
DQ20
DQ21
DQ22
DQ23
V
DD
A6
A8
V
SS
A9
A10
V
DD
CAS2#
CAS3#
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
SDA
V
DD
PIN
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
BACK
RFU
V
SS
RSVD
RSVD
V
DD
DQ48
DQ49
DQ50
DQ51
V
SS
DQ52
DQ53
DQ54
DQ55
V
DD
A7
A11
V
SS
NC (A12)
NC (A13)
V
DD
CAS6#
CAS7#
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
SCL
V
DD
NOTE:
Symbols in parentheses are not used on these modules but may be used
for other modules in this product family. They are for reference only.
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
Micron is a registered trademark of Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
PART NUMBERS
FPM Operating Mode
PART NUMBER
MT4LDT464HG-x
MT4LDT464HG-x S
MT8LDT864HG-x
MT8LDT864HG-x S
x = speed
CONFIGURATION
4 Meg x 64
4 Meg x 64
8 Meg x 64
8 Meg x 64
REFRESH
Standard
Self
Standard
Self
addresses, strobing CAS# and holding RAS# LOW, thus
executing faster memory cycles. Returning RAS# HIGH
terminates the FAST-PAGE-MODE operation.
EDO PAGE MODE
EDO PAGE MODE, designated by the “X” option, is an
accelerated FAST-PAGE-MODE cycle. The primary advan-
tage of EDO is the availability of data-out even after CAS#
goes back HIGH. EDO provides for CAS# precharge time
(
t
CP) to occur without the output data going invalid. This
elimination of CAS# output control provides for pipelined
READs.
FAST-PAGE-MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO operates as any DRAM READ or FAST-PAGE-
MODE READ, except data will be held valid after CAS#
goes HIGH, as long as RAS# and OE# are held LOW and
WE# is held HIGH. (Refer to the 8 Meg x 8 EDO DRAM data
sheet for additional information on EDO functionality.)
EDO Operating Mode
PART NUMBER
MT4LDT464HG-x X
MT4LDT464HG-x XS
MT8LDT864HG-x X
MT8LDT864HG-x XS
x = speed
CONFIGURATION
4 Meg x 64
4 Meg x 64
8 Meg x 64
8 Meg x 64
REFRESH
Standard
Self
Standard
Self
GENERAL DESCRIPTION
The MT4LDT464H (X)(S) and MT8LDT864H (X)(S) are
randomly accessed 32MB and 64MB memories organized
in a small-outline, x64 configuration. They are specially
processed to operate from 3V to 3.6V for low-voltage memory
systems.
During READ or WRITE cycles, each location is uniquely
addressed via the address bits. The row address is latched
by the RAS# signal, then the column address is latched by
the CAS# signal.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. An EARLY WRITE occurs
when WE# is taken LOW prior to CAS# falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE# falls
after CAS# is taken LOW. During EARLY WRITE cycles,
the data outputs (Q) will remain High-Z, regardless of the
state of OE#. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE# must be taken HIGH to disable the data
outputs prior to applying input data. If a LATE WRITE or
READ-MODIFY-WRITE is attempted while keeping OE#
LOW, no WRITE will occur, and the data outputs will drive
read data from the access location.
REFRESH
Memory cell data is retained in its correct state by main-
taining power and executing any RAS# cycle (READ,
WRITE) or RAS# refresh cycle (RAS#-ONLY, CBR or HID-
DEN) so that all combinations of RAS# addresses are ex-
ecuted at least every
t
REF, regardless of sequence. The CBR
REFRESH cycle will invoke the internal refresh counter for
automatic RAS# addressing.
An optional self refresh mode is also available on the “S”
version. The “S” option allows the user the choice of a fully
static, low-power data retention mode or a dynamic refresh
mode at the extended refresh period of 128ms, or 125µs per
row when using distributed CBR REFESH. The optional
self refresh feature is initiated by performing a CBR RE-
FRESH cycle and holding RAS# LOW for the specified
t
RASS.
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of
t
RPS. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS# LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence, a
burst refresh is not required upon exiting self refresh.
However, if the DRAM controller utilizes a RAS#-ONLY or
burst refresh sequence, all 1,240 rows must be refreshed
within the average internal refresh rate, prior to the re-
sumption of normal operation.
FAST PAGE MODE
FAST-PAGE-MODE operations allow faster data opera-
tions (READ or WRITE) within a row-address-defined
page boundary. The FAST-PAGE-MODE cycle is always
initiated with a row address strobed in by RAS#, followed
by a column address strobed in by CAS#. Additional col-
umns may be accessed by providing valid column
STANDBY
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS# HIGH time.
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
SERIAL PRESENCE-DETECT OPERATION
This module family incorporates serial presence-detect
(SPD). The SPD function is implemented using a 2,048-bit
EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to
identify the module type and various DRAM organizations
and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/
WRITE operations between the master (system logic) and
the slave EEPROM device (DIMM) occur via a standard IIC
bus using the DIMM’s SCL (clock) and SDA (data) signals.
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved
for indicating start and stop conditions (Figures 1 and 2).
SPD START CONDITION
All commands are preceded by the start condition, which
is a HIGH-to-LOW transition of SDA when SCL is HIGH.
The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met.
SPD STOP CONDITION
All communications are terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the SPD
device into standby power mode.
SPD ACKNOWLEDGE
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to acknowledge that it received the eight bits
of data (Figure 3).
The SPD device will always respond with an acknowl-
edge after recognition of a start condition and its slave
address. If both the device and a WRITE operation have
been selected, the SPD device will respond with an ac-
knowledge after the receipt of each subsequent eight-bit
word. In the read mode the SPD device will transmit eight
bits of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the slave will continue
to transmit data. If an acknowledge is not detected, the slave
will terminate further data transmissions and await the
stop condition to return to standby power mode.
SCL
SCL
SDA
SDA
DATA STABLE
DATA
CHANGE
DATA STABLE
Figure 1
DATA VALIDITY
START
BIT
STOP
BIT
Figure 2
DEFINITION OF START AND STOP
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
Figure 3
ACKNOWLEDGE RESPONSE FROM RECEIVER
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
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