8 MEG x 8
EDO DRAM
DRAM
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x8 pinout, timing, functions,
and packages
• 12 row, 11 column addresses (C2) or
13 row, 10 column addresses (P4)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-
compatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data
retention
MT4LC8M8P4, MT4LC8M8C2
For the latest data sheet, please refer to the Micron Web
site:
www.micronsemi.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT (Top View)
32-Pin SOJ
V
CC
DQ0
DQ1
DQ2
DQ3
NC
V
CC
WE#
RAS#
A0
A1
A2
A3
A4
A5
V
CC
32-Pin TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
DQ7
DQ6
DQ5
DQ4
V
SS
CAS#
OE#
NC/A12**
A11
A10
A9
A8
A7
A6
V
SS
OPTIONS
• Refresh Addressing
4,096 (4K) rows
8,192 (8K) rows
• Plastic Packages
32-pin SOJ (400 mil)
32-pin TSOP (400 mil)
• Timing
50ns access
60ns access
• Refresh Rates
Standard Refresh (64ms period)
Self Refresh (128ms period)
MARKING
C2
P4
DJ
TG
-5
-6
None
S*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
V
SS
DQ0
DQ7
DQ1
DQ6
DQ2
DQ5
DQ3
DQ4
NC
Vss
V
CC
CAS#
WE#
RAS#
OE#
NC/A12**
A0
A1
A11
A2
A10
A3
A9
A4
A8
A5
A7
V
CC
A6
V
SS
**NC on C2 version and A12 on P4 version
8 MEG x 8 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC8M8C2DJ-x
MT4LC8M8C2DJ-x S
MT4LC8M8C2TG-x
MT4LC8M8C2TG-x S
MT4LC8M8P4DJ-x
MT4LC8M8P4DJ-x S
MT4LC8M8P4TG-x
MT4LC8M8P4TG-x S
x = speed
REFRESH
ADDRESSING
4K
4K
4K
4K
8K
8K
8K
8K
PACKAGE REFRESH
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
Standard
Self
Standard
Self
Standard
Self
Standard
Self
NOTE:
1. The 8 Meg x 8 EDO DRAM base number
differentiates the offerings in one place—
MT4LC8M8C2. The fifth field distinguishes the
address offerings: C2 designates 4K addresses and
P4 designates 8K addresses.
2. The “#” symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
GENERAL DESCRIPTION
The 8 Meg x 8 DRAM is a high-speed CMOS, dy-
namic random-access memory devices containing
67,108,864 bits and designed to operate from 3V to
3.6V. The MT4LC8M8C2 and MT4LC8M8P4 are func-
tionally organized as 8,388,608 locations containing
eight bits each. The 8,388,608 memory locations are
arranged in 4,096 rows by 2,048 columns on the C2
version and 8,192 rows by 1,024 columns on the P4
version. During READ or WRITE cycles, each location is
MT4LC8M8C2DJ-5
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8 MEG x 8
EDO DRAM
FUNCTIONAL BLOCK DIAGRAM
MT4LC8M8P4 (13 row addresses)
WE#
CAS#
DATA-IN
BUFFER
8
DQ0-
DQ7
CONTROL
LOGIC
NO. 2 CLOCK
GENERATOR
DATA-OUT
BUFFER
8
8
OE#
10
COLUMN-
ADDRESS
BUFFER(10)
REFRESH
CONTROLLER
10
COLUMN
DECODER
1,024
SENSE AMPLIFIERS
I/O GATING
1,024 x 8
8
A0-
A12
REFRESH
COUNTER
ROW SELECT
13
13
ROW-
ADDRESS
BUFFERS (13)
COMPLEMENT
SELECT
ROW
DECODER
13
8,192
8,192 x 8
8,192 x 1,024 x 8
MEMORY
ARRAY
RAS#
NO. 1 CLOCK
GENERATOR
V
DD
V
SS
FUNCTIONAL BLOCK DIAGRAM
MT4LC8M8C2 (12 row addresses)
WE#
CAS#
DATA-IN
BUFFER
8
DQ0-
DQ7
CONTROL
LOGIC
NO. 2 CLOCK
GENERATOR
DATA-OUT
BUFFER
8
8
OE#
11
COLUMN-
ADDRESS
BUFFER(11)
REFRESH
CONTROLLER
11
COLUMN
DECODER
2,048
SENSE AMPLIFIERS
I/O GATING
2,048 x 8
8
A0-
A11
REFRESH
COUNTER
ROW SELECT
12
12
ROW-
ADDRESS
BUFFERS (12)
COMPLEMENT
SELECT
ROW
DECODER
12
4,096
4,096 x 8
4,096 x 2,048 x 8
MEMORY
ARRAY
RAS#
NO. 1 CLOCK
GENERATOR
V
DD
V
SS
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8 MEG x 8
EDO DRAM
GENERAL DESCRIPTION (continued)
uniquely addressed via the address bits. First, the row
address is latched by the RAS# signal, then the column
address is latched by CAS#. Both devices provide EDO-
PAGE-MODE operation, allowing for fast successive
data operations (READ, WRITE, or READ-MODIFY-
WRITE) within a given row.
The 8 Meg x 8 DRAM must be refreshed periodically
in order to retain stored data.
EDO PAGE MODE
DRAM READ cycles have traditionally turned the
output buffers off (High-Z) with the rising edge of
CAS#. If CAS# went HIGH and OE# was LOW (active),
the output buffers would be disabled. The 8 Meg x 8
DRAM offers an accelerated page mode cycle by elimi-
nating output disable from CAS# HIGH. This option is
called EDO, and it allows CAS# precharge time (
t
CP) to
occur without the output data going invalid (see READ
and EDO-PAGE-MODE READ waveforms in the noted
appendix).
EDO operates like any DRAM READ or FAST-PAGE-
MODE READ, except data is held valid after CAS#
goes HIGH, as long as RAS# and OE# are held LOW and
WE# is held HIGH. OE# can be brought LOW or HIGH
while CAS# and RAS# are LOW, and the DQs will
transition between valid data and High-Z. Using OE#,
there are two methods to disable the outputs and keep
them disabled during the CAS# HIGH time. The first
method is to have OE# HIGH when CAS# transitions
HIGH and keep OE# HIGH for
t
OEHC thereafter. This
will disable the DQs, and they will remain disabled
(regardless of the state of OE# after that point) until
CAS# falls again. The second method is to have OE#
LOW when CAS# transitions HIGH and then bring OE#
HIGH for a minimum of
t
OEP anytime during the CAS#
HIGH period. This will disable the DQs, and they will
remain disabled (regardless of the state of OE# after that
point) until CAS# falls again (see Figure 1). During
DRAM ACCESS
Each location in the DRAM is uniquely addressable,
as mentioned in the General Description. The data for
each location is accessed via the eight I/O pins (DQ0-
DQ7). A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE occurs
when WE# falls after CAS# is taken LOW. During
EARLY WRITE cycles, the data outputs (Q) will remain
High-Z, regardless of the state of OE#. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE# must be
taken HIGH to disable the data outputs prior to apply-
ing input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping OE# LOW, no write
will occur, and the data outputs will drive read data
from the accessed location.
RAS#
V IH
V IL
CAS#
V IH
V IL
ADDR
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ V IOH
V IOL
OPEN
VALID DATA (A)
tOD
tOES
VALID DATA (A)
VALID DATA (B)
tOD
tOEHC
VALID DATA (C)
tOD
VALID DATA (D)
OE#
V IH
V IL
tOE
tOEP
The DQs go back to
Low-Z if
t
OES is met.
The DQs remain High-Z
until the next CAS# cycle
if
t
OEHC is met.
The DQs remain High-Z
until the next CAS# cycle
if
t
OEP is met.
DON’T CARE
UNDEFINED
Figure 1
OE# CONTROL of DQs
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8 MEG x 8
EDO DRAM
EDO PAGE MODE (continued)
other cycles, the outputs are disabled at
t
OFF time after
RAS# and CAS# are HIGH or at
t
WHZ after WE# transi-
tions LOW. The
t
OFF time is referenced from the rising
edge of RAS# or CAS#, whichever occurs last. WE# can
also perform the function of disabling the output
drivers under certain conditions, as shown in Figure 2.
EDO-PAGE-MODE operations are always initiated
with a row address strobed in by the RAS# signal,
followed by a column address strobed in by CAS#,
just like for single location accesses. However, subse-
quent column locations within the row may then be
accessed at the page mode cycle time. This is accom-
plished by cycling CAS# while holding RAS# LOW and
entering new column addresses with each CAS# cycle.
Returning RAS# HIGH terminates the EDO-PAGE-MODE
operation.
covers all rows. The CBR REFRESH cycle will invoke the
internal refresh counter for automatic RAS# address-
ing. Alternatively, RAS#-ONLY REFRESH capability is
inherently provided. However, with this method, some
compatibility issues may become apparent. For ex-
ample, both C2 and P4 versions require 4,096 CBR
REFRESH cycles, yet each requires a different number of
RAS#-ONLY REFRESH cycles (C2 = 4,096 and P4 =
8,192). JEDEC strongly recommends the use of CBR
REFRESH for this device.
An optional self refresh mode is also available on the
“S” version. The self refresh feature is initiated by
performing a CBR REFRESH cycle and holding RAS#
LOW for the specified
t
RASS. The “S” option allows for
an extended period of 128ms, or 31.25µs per row for a
4K refresh and 15.625µs per row for an 8K refresh, when
using a distributed CBR REFRESH. This refresh rate can
be applied during normal operation, as well as during
a standby or battery backup mode.
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of
t
RPS. This delay allows for
the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH
transition. If the DRAM controller uses a distributed
CBR refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM
controller utilizes a RAS#-ONLY or burst CBR refresh
sequence, all 1,024 rows must be refreshed using a
minimum
t
RC refresh rate prior to resuming normal
operation.
DRAM REFRESH
The supply voltage must be maintained at the speci-
fied levels, and the refresh requirements must be met in
order to retain stored data in the DRAM. The refresh
requirements are met by refreshing all 8,192 rows (P4)
or all 4,096 rows (C2) in the DRAM array at least once
every 64ms. The recommended procedure is to execute
4,096 CBR REFRESH cycles, either uniformly spaced or
grouped in bursts, every 64ms. The MT4LC8M8P4 in-
ternally refreshes two rows for every CBR cycle, whereas
the MT4LC8M8C2 refreshes one row for every CBR
cycle. So with either device, executing 4,096 CBR cycles
RAS#
V IH
V IL
CAS#
V IH
V IL
ADDR
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ V IOH
V IOL
OPEN
VALID DATA (A)
t
WHZ
VALID DATA (B)
tWHZ
INPUT DATA (C)
WE#
V IH
V IL
V IH
V IL
tWPZ
OE#
The DQs go to High-Z if WE# falls and, if
t
WPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
DON’T CARE
UNDEFINED
Figure 2
WE# CONTROL of DQs
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8 MEG x 8
EDO DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
CC
Relative to V
SS
................ -1V to +4.6V
Voltage on NC, Inputs or I/O Pins
Relative to V
SS
....................................... -1V to +4.6V
Operating Temperature, T
A
(ambient) ... 0°C to +70°C
Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ................................................... 1W
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Note: 1) (V
CC
= +3.3V ±0.3V)
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE:
Valid Logic 1; All inputs, I/Os and any NC
INPUT LOW VOLTAGE:
Valid Logic 0; All inputs, I/Os and any NC
INPUT LEAKAGE CURRENT:
Any input at V
IN
(0V
£
V
IN
£
V
CC
+ 0.3V);
All other pins not under test = 0V
OUTPUT HIGH VOLTAGE:
I
OUT
= -2mA
OUTPUT LOW VOLTAGE:
I
OUT
= 2mA
OUTPUT LEAKAGE CURRENT:
Any output at V
OUT
(0V
£
V
OUT
£
V
CC
+ 0.3V);
DQ is disabled and in High-Z state
SYMBOL
V
CC
V
IH
V
IL
I
I
MIN
3
2
-0.3
-2
MAX
3.6
V
CC
+ 0.3
0.8
2
UNITS NOTES
V
V
V
µA
26
26
27
V
OH
V
OL
I
OZ
2.4
–
-5
–
0.4
5
V
V
µA
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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