TECHNOLOGY, INC.
4 MEG x 4
EDO DRAM
MT4LC4M4E8, MT4C4M4E8
MT4LC4M4E9, MT4C4M4E9
DRAM
FEATURES
• Industry-standard x4 pinout, timing, functions and
packages
• State-of-the-art, high-performance, low-power CMOS
silicon-gate process
• Single power supply (+3.3V
±0.3V
or +5V
±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-
BEFORE-RAS# (CBR)
• Optional Self Refresh (S) for low-power data retention
• 11 row, 11 column addresses (2K refresh) or
12 row, 10 column addresses (4K refresh)
• Extended Data-Out (EDO) PAGE MODE access cycle
• 5V-tolerant inputs and I/Os on 3.3V devices
PIN ASSIGNMENT (Top View)
24/26-Pin SOJ
(DA-2)
V
CC
DQ1
DQ2
WE#
RAS#
*NC/A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
V
SS
DQ4
DQ3
CAS#
OE#
A9
A8
A7
A6
A5
A4
V
SS
24/26-Pin TSOP
(DB-2)
V
CC
DQ1
DQ2
WE#
RAS#
*NC/A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
V
SS
DQ4
DQ3
CAS#
OE#
A9
A8
A7
A6
A5
A4
V
SS
OPTIONS
• Voltages
3.3V
5V
• Refresh Addressing
2,048 (i.e. 2K) Rows
4,096 (i.e. 4K) Rows
• Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
• Timing
50ns access
60ns access
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
MARKING
LC
C
E8
E9
DJ
TG
-5
-6
None
S
* NC on 2K refresh and A11 on 4K refresh options.
Note:
The “#” symbol indicates signal is active LOW.
4 MEG x 4 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC4M4E8DJ
MT4LC4M4E8DJS
MT4LC4M4E8TG
MT4LC4M4E8TGS
MT4LC4M4E9DJ
MT4LC4M4E9DJS
MT4LC4M4E9TG
MT4LC4M4E9TGS
MT4C4M4E8DJ
MT4C4M4E8DJS
MT4C4M4E8TG
MT4C4M4E8TGS
MT4C4M4E9DJ
MT4C4M4E9DJS
MT4C4M4E9TG
MT4C4M4E9TGS
Vcc
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
5V
5V
5V
5V
5V
5V
5V
5V
REFRESH
2K
2K
2K
2K
4K
4K
4K
4K
2K
2K
2K
2K
4K
4K
4K
4K
PACKAGE
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
REFRESH
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
• Part Number Example: MT4LC4M4E8DJ-6
Note:
The 4 Meg x 4 EDO DRAM base number differentiates the offerings in
two places -
MT4LC4M4E8.
The third field distinguishes the low voltage
offering: LC designates V
CC
= 3.3V and C designates V
CC
= 5V. The fifth field
distinguishes various options: E8 designates a 2K refresh and E9 designates a
4K refresh for EDO DRAMs.
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
GENERAL DESCRIPTION
The 4 Meg x 4 DRAM is a randomly accessed, solid-state
memory containing 16,777,216 bits organized in a x4 con-
figuration. RAS# is used to latch the row address (first 11
bits for 2K and first 12 bits for 4K). Once the page has been
opened by RAS#, CAS# is used to latch the column address
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4
EDO DRAM
GENERAL DESCRIPTION (continued)
(the latter 11 bits for 2K and the latter 10 bits for 4K, address
pins A10 and A11 are “don’t care”). READ and WRITE
cycles are selected with the WE# input.
A logic HIGH on WE# dictates READ mode, while a logic
LOW on WE# dictates WRITE mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. An EARLY WRITE occurs
when WE# is taken LOW prior to CAS# falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE# falls
after CAS# is taken LOW. During EARLY WRITE cycles,
the data outputs (Q) will remain High-Z regardless of the
state of OE#. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE# must be taken HIGH to disable the data
outputs prior to applying input data. If a LATE WRITE or
READ-MODIFY-WRITE is attempted while keeping OE#
LOW, no write will occur, and the data outputs will drive
read data from the accessed location.
The four data inputs and the four data outputs are routed
through four pins using common I/O, and pin direction is
controlled by WE# and OE#.
with a row address strobed-in by RAS#, followed by a
column address strobed-in by CAS#. CAS# may be
toggled-in by holding RAS# LOW and strobing-in different
column addresses, thus executing faster memory cycles.
Returning RAS# HIGH terminates the PAGE MODE of
operation, i.e., closes the page.
EDO PAGE MODE
The 4 Meg x 4 EDO DRAM provides EDO PAGE MODE,
which is an accelerated FAST PAGE MODE cycle. The
primary advantage of EDO is the availability of data-out
even after CAS# returns HIGH. EDO allows CAS# precharge
time (
t
CP) to occur without the output data going invalid.
This elimination of CAS# output control allows pipeline
READs.
FAST PAGE MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO PAGE MODE DRAMs operate like FAST
PAGE MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, pro-
vided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z (refer to
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row address-
defined page boundary. The PAGE cycle is always initiated
RAS#
V IH
V IL
CAS#
ADDR
DQ V IOH
V IOL
, ,,,,, ,,,,, ,,,,, ,,,,
,, ,,
,
,, , , ,
V IH
V IL
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
OPEN
V IH
V IL
OE#
,,
VALID DATA (A)
t OD
VALID DATA (A)
t OES
t OE
,,, ,,
VALID DATA (B)
t OD
t OEHC
VALID DATA (C)
t OD
,
VALID DATA (D)
t OEP
The DQs go back to
Low-Z if
t
OES is met.
The DQs remain High-Z
until the next CAS# cycle
if
t
OEHC is met.
The DQs remain High-Z
until the next CAS# cycle
if
t
OEP is met.
,
,
,,
,,
DON’T CARE
UNDEFINED
Figure 1
OE# CONTROL OF DQs
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4
EDO DRAM
fresh cycle and holding RAS# LOW for the specified
t
RASS.
Additionally, the “S” option allows for an extended refresh
period of 128ms, or 31.25µs per row for a 4K refresh and
62.5µs per row for a 2K refresh if using distributed CBR
Refresh. This refresh rate can be applied during normal
operation, as well as during a standby or BATTERY BACKUP
mode.
The Self Refresh mode is terminated by driving RAS#
HIGH for a minimum time of
t
RPS. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS# LOW-to-HIGH transition.
If the DRAM controller uses a distributed refresh se-
quence, a burst refresh is not required upon exiting
Self Refresh. However, if the DRAM controller utilizes a
RAS#- ONLY or burst refresh sequence, all rows must be
refreshed within the average internal refresh rate, prior to
the resumption of normal operation.
Figure 1). WE# can also perform the function of disabling
the output devices under certain conditions, as shown in
Figure 2.
During an application, if the DQ outputs are wire OR’d,
OE# must be used to disable idle banks of DRAMs. Alter-
natively, pulsing WE# to the idle banks during CAS# high
time will also High-Z the outputs. Independent of OE#
control, the outputs will disable after
t
OFF, which is refer-
enced from the rising edge of RAS# or CAS#, whichever
occurs last.
REFRESH
Preserve correct memory cell data by maintaining power
and executing any RAS# cycle (READ, WRITE) or RAS#
refresh cycle (RAS#-ONLY, CBR or HIDDEN) so that all
combinations of RAS# addresses (2,048 for 2K and 4,096 for
4K) are executed within
t
REF (MAX), regardless of se-
quence. The CBR and Self Refresh cycles will invoke the
internal refresh counter for automatic RAS# addressing.
An optional Self Refresh mode is also available on the S
version. The “S” option allows the user the choice of a fully
static, low-power data retention mode or a dynamic refresh
mode at the extended refresh period of 128ms. The optional
Self Refresh feature is initiated by performing a CBR Re-
STANDBY
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
The chip is preconditioned for the next cycle during the
RAS# HIGH time.
RAS#
CAS#
ADDR
DQ V IOH
V IOL
, ,,,,,, ,,, , ,,,,
,, ,,
,
,
, , , ,
,,
,
,,
V IH
V IL
V IH
V IL
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
OPEN
V IH
V IL
V IH
V IL
WE#
,,
VALID DATA (A)
t WHZ
t WPZ
,
VALID DATA (B)
INPUT DATA (C)
t WHZ
,,
OE#
The DQs go to High-Z if WE# falls and, if
t
WPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
Figure 2
WE# CONTROL OF DQs
,,
,,
,
,,
DON’T CARE
UNDEFINED
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4
EDO DRAM
FUNCTIONAL BLOCK DIAGRAM - 2K REFRESH
WE#
CAS#
DATA-IN
BUFFER
4
NO. 2 CLOCK
GENERATOR
DATA-OUT
BUFFER
4
4
DQ1
DQ2
DQ3
DQ4
OE#
COLUMN
ADDRESS
BUFFER(11)
REFRESH
CONTROLLER
COMPLEMENT
SELECT
11
11
ROW
ADDRESS
BUFFERS (11)
ROW SELECT
(2 of 4096)
11
ROW
DECODER
2048
2048
2048
2048
2048
4096 x 1024 x 4
MEMORY
ARRAY
RAS#
NO. 1 CLOCK
GENERATOR
ROW TRANSFER
ROW TRANSFER
(1 OF 2)
(1 OF 2)
V
DD
V
SS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
11
10
1
COLUMN
DECODER
1024
4
SENSE AMPLIFIERS
I/O GATING
1024
REFRESH
COUNTER
FUNCTIONAL BLOCK DIAGRAM - 4K REFRESH
WE#
CAS#
DATA-IN
BUFFER
4
NO. 2 CLOCK
GENERATOR
DATA-OUT
BUFFER
4
4
DQ1
DQ2
DQ3
DQ4
OE#
COLUMN
ADDRESS
BUFFER(10)
REFRESH
CONTROLLER
COMPLEMENT
SELECT
12
ROW SELECT
(1 of 4096)
ROW
DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
10
10
COLUMN
DECODER
1024
4
SENSE AMPLIFIERS
I/O GATING
1024
REFRESH
COUNTER
4096 x 1024 x 4
MEMORY
ARRAY
12
ROW
ADDRESS
BUFFERS (12)
4096
4096
12
4096
RAS#
NO. 1 CLOCK
GENERATOR
V
DD
V
SS
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
4 MEG x 4
EDO DRAM
TRUTH TABLE
ADDRESSES
FUNCTION
Standby
READ
EARLY WRITE
READ WRITE
EDO-PAGE-MODE
READ
EDO-PAGE-MODE
EARLY WRITE
EDO-PAGE-MODE
READ-WRITE
HIDDEN
REFRESH
RAS#-ONLY REFRESH
CBR REFRESH
SELF REFRESH
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
Any Cycle
1st Cycle
2nd Cycle
READ
WRITE
RAS#
H
L
L
L
L
L
L
L
L
L
L
L→H→L
L→H→L
L
H→L
H→L
CAS#
H→X
L
L
L
H→L
H→L
H→L
H→L
L→H
H→L
H→L
L
L
H
L
L
WE#
X
H
L
H→L
H
H
L
L
H
H→L
H→L
H
L
X
H
H
OE#
X
L
X
L→H
L
L
X
X
L
L→H
L→H
L
X
X
X
X
t
R
t
C
DATA-IN/OUT
DQ1-DQ4
High-Z
Data-Out
Data-In
Data-Out, Data-In
Data-Out
Data-Out
Data-In
Data-In
Data-Out
Data-Out, Data-In
Data-Out, Data-In
Data-Out
Data-In
High-Z
High-Z
High-Z
X
ROW
ROW
ROW
ROW
n/a
ROW
n/a
n/a
ROW
n/a
ROW
ROW
ROW
X
X
X
COL
COL
COL
COL
COL
COL
COL
n/a
COL
COL
COL
COL
n/a
X
X
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
实时操作系统RTOS
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
