AS8202NF
TTP-C2NF Communication Controller
D a ta S he e t
1 General Description
The AS8202NF communication controller is an
integrated device supporting serial communication
according to the TTP specification version 1.1. It
performs all communication tasks such as reception and
transmission of messages in a TTP cluster without
interaction of the host CPU. TTP provides mechanisms
that allow the deployment in high-dependability
distributed real-time systems. It provides the following
services:
Predictable transmission of messages with minimal
jitter
Fault-tolerant distributed clock synchronization
Consistent membership service with small delay
Masking of single faults
40 MHz main clock with support for 10 MHz crystal,
10 MHz oscillator or 40 MHz oscillator
16 MHz bus guardian clock with support for 16 MHz
crystal or 16 MHz oscillator
Single power supply 3.3V, 0.35µm CMOS process
Full automotive temperature range (-40ºC to 125ºC)
16k x 16 SRAM for message, status, control area
(communication network interface) and for
scheduling information (MEDL)
4k x 16 (plus parity) instruction code RAM for
protocol execution code
Data sheet conforms to protocol revision 2.04
16k x 16 instruction code ROM containing startup
execution code and deprecated protocol code
revision 1.00
16 Bit non-multiplexed asynchronous host CPU
interface
16 Bit RISC architecture
Software tools, design support, development boards
available (www.tttech.com)
Certification support package according to RTCA/
DO-254 DAL A available (www.tttech.com)
80 pin LQFP80 Package
2 Key Features
Dual-channel controller for redundant data transfers
Dedicated controller supporting TTP (time-triggered
protocol class C)
Suited for dependable distributed real-time systems
with guaranteed response time
Asynchronous data rate up to 5 Mbit/s (MFM/
Manchester)
Synchronous data rate 5 to 25 Mbit/s
Bus interface (speed, encoding) for each channel
selectable independently
Figure 1. Block Diagram
Host
Processor
Interface
D[15:0]
A[11:0]
CEB
OEB
WEB
READYB
INTB
LED[2:0]
RAM_CLK_TESTSE
USE_RAM_CLK
3 Applications
Application fields: automotive (by-wire braking, steering,
vehicle dynamics control, drive train control), aerospace
(aircraft electronic systems), industrial systems, railway
systems.
Receiver
RxD[1:0]
RXCLK[1:0]
RxDV[1:0]
RXER[1:0]
XIN1
XOUT1
TTP Bus
Media
Drivers
Communication
network
interface
(CNI)
TTP
Protocol
processor core
Bus guardian
AS8202NF
Transmitter
TxD[1:0]
CTS[1:0]
TxCLK[1:0]
RAM_CLK_TESTSE
FTEST
Test
STEST
Interface
FIDIS
TTEST
Quartz or
Oscillator
XIN0
XOUT0
PLLOFF
RESETB
Instruction
memory
RAM & ROM
Test
Interface
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TTTech Computertechnik AG
Revision 2.1
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AS8202NF TTP-C2NF
Data Sheet
- A p p l i c a t i o n s
Contents
1 General Description ...............................................................................................................................1
2 Key Features ...........................................................................................................................................1
3 Applications ............................................................................................................................................1
4 Pin Assignments ....................................................................................................................................3
4.1 Pin Descriptions ................................................................................................................................................3
5 Absolute Maximum Ratings ..................................................................................................................6
6 Electrical Characteristics.......................................................................................................................7
7 Detailed Description ...............................................................................................................................9
7.1 Host CPU Interface ...........................................................................................................................................9
7.1.1 Synchronous READYB Generation.......................................................................................................12
7.2 Reset and Oscillator ........................................................................................................................................13
7.2.1
7.2.2
7.2.3
7.2.4
External Reset Signal............................................................................................................................13
Integrated Power-On Reset ..................................................................................................................13
Oscillator Circuitry .................................................................................................................................13
Build-up Characteristics ........................................................................................................................14
7.3 TTP Bus Interface ...........................................................................................................................................15
7.4 TTP Asynchronous Bus Interface....................................................................................................................15
7.5 TTP Synchronous Bus Interface .....................................................................................................................16
7.6 Test Interface ...................................................................................................................................................16
7.7 LED Signals.....................................................................................................................................................17
8 Package Drawings and Markings........................................................................................................ 18
9 Ordering Information............................................................................................................................19
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AS8202NF TTP-C2NF
Data Sheet
- P i n A s s i g n m e n t s
4 Pin Assignments
Figure 2. Pin Assignments LQFP80 Package
VSSPLL
READYB
WEB
OEB
CEB
VSS
VDD
VSSBG
XIN1
XOUT1
VDDBG
D15
D14
D13
D12
D11
D10
D9
D8
TTEST
80
1
nc
XIN0
XOUT0
VDDPLL
TXD0
CTS0
TXCLK0
RXER0
RXCLK0
RXDV0
RXD0
VDD
VSS
TXD1
CTS1
TXCLK1
RXER1
RXCLK1
RXDV1
RXD1
20
21
61
60
VSS
VDD
D7
D6
D5
D4
D3
D2
D1
D0
VSS
VDD
A11
A10
A9
A8
A7
A6
A5
VSS
41
RAM_CLK_TESTSE
STEST
PLLOFF
FTEST
FIDIS
RESETB
nc
INTB
VDD
VSS
LED0
LED1
LED2
USE_RAM_CLK
A0
A1
A2
A3
A4
nc
40
AS8202NF
TTP
Communications
Controller
(TOP VIEW)
Pin Descriptions
Table 1. Pin Descriptions
Pin Name
V
DD
V
SS
V
DDBG
V
SSBG
V
DDPLL
V
SSPLL
RAM_CLK_T
ESTSE
STEST
FTEST
FIDIS
TTEST
USE_RAM_C
LK
Pin Number
12,29,49,59,
74
13,30,41,50,
60,75
70
73
4
80
21
22
24
25
61
34
Dir
P
P
P
P
P
P
I
PD
I
PD
I
PD
I
PD
I
PU
I
PD
Description
Positive Power Supply
Negative Power Supply
Positive Power Supply for Bus Guardian (connect to V
DD
)
Negative Power Supply for Bus Guardian (connect to V
SS
)
Positive Power Supply for Main Clock PLL (connect to V
DD
)
Negative Power Supply for Main Clock PLL (connect to V
SS
)
RAM_CLK when STEST=0 and USE_RAM_CLK=1, else Test Input,
connect to V
SS
if not used
Test Input, connect to V
SS
Test Input, connect to V
SS
Test Input, connect to V
SS
Test Input, connect to V
DD
RAM_CLK Pin Enable, connect to V
SS
if not used
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AS8202NF TTP-C2NF
Data Sheet
- P i n A s s i g n m e n t s
Table 1. Pin Descriptions
Pin Name
XIN0
XOUT0
PLLOFF
XIN1
XOUT1
RESETB
TxD0
CTS0
RxD0
TxCLK0
RxER0
RxCLK0
RxDV0
TxD1
CTS1
RxD1
TxCLK1
RXER1
RXCLK1
RxDV1
A[11:0]
D[15:0]
CEB
OEB
WEB
READYB
INTB
LED[2:0]
nc
Pin Number
2
3
23
72
71
26
5
6
11
7
8
9
10
14
15
20
16
17
18
19
48-42, 39-35
69-62, 58-51
76
77
78
79
28
33-31
1, 27, 40
Dir
A
A
I
PD
A
A
I
PU
O
PU
O
PD
I
PU
I
PD
I
PU
I
PD
I
PU
O
PU
O
PD
I
PU
I
PD
I
PU
I
PD
I
PU
I
I/O
I
PU
I
PU
I
PU
O
PU
O
PU
O
PD
Description
Main Clock: Analog CMOS Oscillator Input, use as input when
providing external clock
Main Clock: Analog CMOS Oscillator Output, leave open when
providing external clock
Main Clock PLL Disable Pin, connect to V
SS
when providing 10 MHz
crystal for enabling the internal PLL
Bus Guardian Clock: Analog CMOS Oscillator Input, use as input
when providing external clock
Bus Guardian Clock: Analog CMOS Oscillator Output, leave open
when providing external clock
Main Reset Input, active low
TTP Bus Channel 0: Transmit Data
TTP Bus Channel 0: Transmit Enable
TTP Bus Channel 0: Receive Data
TTP Bus Channel 0: Transmit Clock (MII mode)
TTP Bus Channel 0: Receive Error (MII mode)
TTP Bus Channel 0: Receive Clock (MII mode)
TTP Bus Channel 0: Receive Data Valid (MII mode)
TTP Bus Channel 1: Transmit Data
TTP Bus Channel 1: Transmit Enable
TTP Bus Channel 1: Receive Data
TTP Bus Channel 1: Transmit Clock (MII mode)
TTP Bus Channel 1: Receive Error (MII mode)
TTP Bus Channel 1: Receive Clock (MII mode)
TTP Bus Channel 1: Receive Data Valid (MII mode)
Host Interface (CNI) Address Bus
Host Interface (CNI) Data Bus, tristate
Host Interface (CNI) Chip Enable, active low
Host interface (CNI) output enable, active low
Host interface (CNI) write enable, active low
Host interface (CNI) transfer finish signal, active low, open drain
Host interface (CNI) time signal (interrupt), active low, open drain
Configurable generic output port
Not connected, leave open
2
1
1. The device is addressed at 16-bit data word boundaries. If the device is connected to a CPU with a byte-
granular address bus, remember that A[11:0] of the AS8202NF device has to be connected to A[12:1] of the
CPU (considering a little endian CPU address bus)
2. At de-assertion READYB is driven to the inactive value (high) for a configurable time.
Table 2. Pin Directions
Dir
I
I
PU
I
PD
I/O
O
PU
Description
TTL Input
TTL Input with Internal Weak Pull-Up
TTL Input with Internal Weak Pull-Down
TTL Input/Output with Tristate
TTL Output with Internal Weak Pull-Up at Tristate
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AS8202NF TTP-C2NF
Data Sheet
- P i n A s s i g n m e n t s
Table 2. Pin Directions
Dir
O
PD
A
P
Description
TTL Output with Internal Weak Pull-Down at Tristate
Analog CMOS Pin
Power Pin
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