AS3524 C21 / C22
Data Sheet, Confidential
austriamicrosystems
Datasheet, Confidential
AS3524
Advanced Audio Processor System
å
1
Description
Key Features
1.1
Digital Core
Embedded 32-Bit RISC Controller
The AS3524 implements a highly flexible and fully integrated digital
audio processor system combining strong calculating power and
high performance interfaces commonly used within audio player
systems.
Using advanced 0.13µm process technology and large on chip
RAM leads to outstanding low power consumption of 0.3 mW/MHz
for the ARM922T microcontroller core and 0.6 mW/MHz for the
overall system measured with a typical MP3 player SW application.
Based on a powerful ARM9TDMI capable of performing up to
200MIPS it is suited to run MP3, AAC, WMA, OGG… decoders and
encoders and, in addition, it can perform extensive user interfaces,
motion graphics support, video playback and much more.
The AS3524 SOC (system-on-a-Chip) features dedicated high
speed interfaces for ATA IDE, USB2.0 HS-OTG and SDRAM
ensuring maximum performance for download, upload, and
playback.
Furthermore interfaces for NAND flashes, MMC/SD cards and
Memory Stick ensure most flexible system design possibilities.
Hardware support for parallel interfaces lower the CPU load serving
complex and/or colour user interfaces.
Additional serial high-speed data and control interfaces guarantee
the connection to other peripherals and or processors in the system.
Two independently programmable PLLs generate the required
frequencies for audio playback/recording, for the processor core
and for the USB interface at the same time.
•
ARM922TDMI RISC CPU
•
2.5Mbit on-chip RAM
•
1Mbit on chip ROM
•
Clock speed max. 250MHz (200MIPS)
•
Standard JTAG interface
USB 2.0 HS & OTG Interface
•
Up to 480Mbit/s transfer speed
•
USB 2.0 HS/FS physical inlcuding OTG support
•
USB 2.0 HS/FS digital core including OTG host
•
Dedicated dual port buffer RAM
•
DMA bus master functionality
IDE Host Controller
•
Supporting Ultra ATA 33/66/100/133 modes
•
Programmable IO and Multi-word DMA capability
•
Dedicated dual port buffer RAM
•
DMA bus master functionality
External Memory Controller
•
Dynamic memory interface
•
Asynchronous static memory
•
DMA bus master functionality
DMA Controller
•
Single Master DMA controller
•
2 DMA channels possible at the same time
•
16 DMA requests supported
Interrupt Controller
•
Support for 32 standard interrupts
•
Support for 16 vectored IRQ interrupts
Audio Subsystem Interface
•
Dedicated 2 wire serial control master
•
I2S input and output with dual port buffer RAM
Nand Flash Interface
•
•
•
8 and 16bit flash support
3, 4 & 5 byte address support
hardware ECC
© 2003-2010, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
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AS3524 C21 / C22
Data Sheet, Confidential
MMC/SD Interface
•
MMC/SD Card host for multiple card support
•
4 data line support for SD cards
MS / MS Pro Interface
•
Dedicated dual port buffer RAM
Display Interface
•
Serial and parallel controller supported
•
On chip hardware acceleration
Synchronous Serial Interface
•
Master and slave operation
•
8 and 16 bit support
•
Several protocol standards supported
I2S Interface
•
Input multiplexed with audio subsystem
•
selectable SPDIF input conversion
•
Dedicated dual port buffer RAM
2 Wire Serial Control Interface
•
Master and slave operation
•
Standard and fast mode support
General Purpose IO Interface
•
4x 8-bit ports
Multiple Boot Options
•
•
•
Selection of internal ROM or external boot device
Internal boot loader supporting boot from external
NorFlash, NandFlash, IDE, SPI host
Internal USB boot loader with USB promer supporting
initial factory programming and firmware update
austriamicrosystems
2
•
•
•
•
Application
Portable Digital Audio Player and Recorder
Portable Digital Media Player
PDA
Smartphone
© 2003-2010, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
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AS3524 C21 / C22
Data Sheet, Confidential
austriamicrosystems
3
Figure 1
Block Diagram
AS3524 Block Diagram
© 2003-2010, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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AS3524 C21 / C22
Data Sheet, Confidential
austriamicrosystems
1
DESCRIPTION ........................................................................................................1
KEY FEATURES.............................................................................................................1
1.1
Digital Core....................................................................................................................................................... 1
2
3
4
4.1
APPLICATION ........................................................................................................2
BLOCK DIAGRAM..................................................................................................3
ELECTRICAL SPECIFICATIONS...........................................................................8
Absolute Maximum Ratings ............................................................................................................................ 8
4.2 Operating Conditions....................................................................................................................................... 9
4.2.1
Supply Voltages .................................................................................................................................... 9
4.2.2
Operating Currents .............................................................................................................................. 10
4.2.3
Temperature Range ............................................................................................................................. 10
4.2.4
Start-up Sequence for Supply Voltages............................................................................................... 11
5
DETAILED FUNCTIONAL DESCRIPTIONS.........................................................12
5.1 ARM922-T Processor Core ........................................................................................................................... 12
5.1.1
General ................................................................................................................................................ 12
5.1.2
Block Diagrams................................................................................................................................... 13
5.1.3
ARM922T Details ............................................................................................................................... 14
5.1.4
ARM V4T Architecture ...................................................................................................................... 14
5.1.5
JTAG Interface.................................................................................................................................... 16
5.1.6
Boot Concept....................................................................................................................................... 17
5.2 AHB Peripheral Blocks.................................................................................................................................. 19
5.2.1
2.5 MBIT RAM Main Memory........................................................................................................... 19
5.2.2
On-Chip ROM..................................................................................................................................... 20
5.2.3
VIC – Vectored Interrupt Controller ................................................................................................... 20
5.2.4
SMDMAC - Single master DMAC ..................................................................................................... 23
5.2.5
Multi Port Memory Controller (MPMC)............................................................................................. 25
5.2.6
IDE Interface....................................................................................................................................... 26
5.2.7
USB 2.0 HS OTG interface................................................................................................................. 29
5.2.8
Memory Stick / Memory Stick Pro Interface ...................................................................................... 34
5.3 APB Peripheral Block .................................................................................................................................... 36
5.3.1
Timers ................................................................................................................................................. 36
5.3.2
Watchdog Unit .................................................................................................................................... 40
5.3.3
SSP – Synchronous Serial Port ........................................................................................................... 43
5.3.4
GPIO - General purpose input/output ports......................................................................................... 45
5.3.5
MCI – SD / MMC Card Interface ....................................................................................................... 47
5.3.6
I2cAudMas - I2C audio master interface ............................................................................................ 48
5.3.7
I2CMSI - I2C master/slave interface................................................................................................... 49
5.3.8
I2SIN - I2S input interface .................................................................................................................. 50
5.3.9
SPDIF interface................................................................................................................................... 56
5.3.10
I2SOUT - I2S output interface ............................................................................................................ 57
© 2003-2010, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
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AS3524 C21 / C22
Data Sheet, Confidential
austriamicrosystems
5.3.11
5.3.12
5.3.13
5.3.14
5.3.15
NAND Flash Interface ........................................................................................................................ 63
DBOP - Data Block Output Port ......................................................................................................... 74
UART – Universal Asynchronous Receiver/Transmitter.................................................................... 84
CGU - Clock generation unit .............................................................................................................. 91
CCU - Chip Control Unit .................................................................................................................. 105
6
6.1
PINOUT AND PACKAGING ...............................................................................110
Package Variants.......................................................................................................................................... 110
6.2 CTBGA180 Package Drawings ................................................................................................................... 110
6.2.1
Marking............................................................................................................................................. 110
6.2.2
CTBGA180 Package Ball-out ........................................................................................................... 111
6.2.3
CTBGA180 Ball List ........................................................................................................................ 111
6.3 Pad Cell Description..................................................................................................................................... 119
6.3.1
Digital Pads ....................................................................................................................................... 119
7
7.1
APPENDIX ..........................................................................................................120
Memory MAP ............................................................................................................................................... 120
7.2 Register definitions....................................................................................................................................... 122
7.2.1
Base Address definitions................................................................................................................... 122
8
9
10
11
ORDERING INFORMATION ...............................................................................123
COPYRIGHT .......................................................................................................124
DISCLAIMER ......................................................................................................124
CONTACT INFORMATION.................................................................................124
© 2003-2010, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
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