Datas heet
AS1506
2 5 6 - Ta p D i g i ta l P o t e n t i o m e t e r w i t h S P I I n t e r f a c e a n d
High Endurance EEPROM
1 General Description
The AS1506 is a linear, 256-tap digital potentiometer
specifically designed to replace discrete/mechanical
potentiometers and is ideal for applications requiring a
low-temperature-coefficient variable resistor, such as
low-drift, programmable gain, and amplifier circuit con-
figurations.
The device is controlled via a 3-wire SPI-compatible
interface and features an internal EEPROM for storing
wiper positions.
Several device variants are available differentiated by
end-to-end resistance as shown in
Table 1
(see also
Ordering Information on page 16).
Table 1. Standard Products
Model
AS1506-10
AS1506-50
AS1506-100
End-to-End Resistance (kΩ)
10
50
100
2 Key Features
!
!
High Endurance: EEPROM up to 10M cycles
High Reliability: EEPROM up to 150 years data
retention @ 85°C
Wiper Position Retained in EEPROM and loaded at
Power-Up
256 Tap Positions
±0.5LSB DNL in Voltage Divider Mode
±0.5LSB INL in Voltage Divider Mode
End-to-End Resistance: 10/50/100kΩ
Low End-to-End Resistance Temperature
Coefficient: 90ppm/ºC
Low-Power Standby Mode: 100nA
5MHz SPI-Compatible Serial Interface
Single-Supply Operation: +2.7V to +5.5V
8-pin TDFN 3x3mm Package
!
!
!
!
!
!
!
!
!
!
The 3-wire SPI-compatible serial interface allows com-
munication at data rates up to 5MHz.The internal
EEPROM stores the last wiper position for initialization
during power-up and a low-power standby mode.
The devices are available in an 8-pin TDFN 3x3mm
package.
3 Applications
The device is ideal for mechanical potentiometer
replacement, low-drift programmable gain amplifiers,
audio volume control, LCD contrast control, and low-drift
programmable filters.
Figure 1. AS1506 - Block Diagram
1
VDD
8-Bit
Shift Register
8
8-Bit
Latch
8
256
8
HIGH
256-Position
Decoder
2
SCLK
3
SDIO
4
CSN
SPI
Interface
Power-
On
Reset
8-Bit
EEPROM
7
WIPER
6
LOW
AS1506
5
GND
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AS1506
Datasheet - P i n o u t
4 Pinout
Pin Assignments
Figure 2. Pin Assignments (Top View)
VDD 1
8 HIGH
SCLK 2
7 WIPER
AS1506
SDIO 3
6 LOW
CSN 4
5 GND
Pin Descriptions
Table 2. Pin Descriptions
Pin Number
1
2
3
4
5
6
7
8
N/A
Description
2.7V to 5.5V Supply Voltage.
Bypass with a 0.1µF capacitor to GND.
Serial Clock Input
Serial Data Input/Output
Active-Low Chip Select
Ground
Low Terminal.
The voltage at this pin can be greater than or less than the voltage at
LOW
pin HIGH. Current can flow into or out of this pin.
Wiper Terminal
WIPER
High Terminal.
The voltage at this pin can be greater than or less than the voltage
HIGH
at pin LOW. Current can flow into or out of this pin.
Exposed Pad The exposed pad is not internally connected. Leave floating.
Pin Name
VDD
SCLK
SDIO
CSN
GND
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AS1506
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in
Table 3
may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in
Electrical Character-
istics on page 4
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 3. Absolute Maximum Ratings
Parameter
V
DD
to GND
All Other Pins to GND
AS1506-10
Maximum Continuous Current into
Pins HIGH, WIPER, and LOW
Electrostatic Discharge
Latch-Up
1
Min
-0.3
-0.3
Max
+7.0
V
DD
+
0.3
Units
V
V
Comments
+0.55
+0.55
+0.55
1
-100
48
-40
-60
+85
+150
+150
100
kV
mA
ºC/W
ºC
ºC
ºC
The reflow peak soldering temperature
(body temperature) specified is in
accordance with
IPC/JEDEC J-STD-020D
“Moisture/Reflow Sensitivity Classification
for Non-Hermetic Solid State Surface
Mount Devices”.
The lead finish for Pb-free leaded
packages is matte tin (100% Sn).
HBM MIL-Std. 883E 3015.7
methods
JEDEC 78
on PCB
mA
AS1506-50
AS1506-100
Thermal Resistance
Θ
JA
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Package Body Temperature
+260
ºC
1. The maximum rating voltage must not be exceeded during Latch-up test of the device.
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AS1506
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
V
DD
= +2.7 to +5.5V, HIGH = V
DD
, LOW = GND, T
AMB
= -40 to +85ºC. Typ values are at V
DD
= +5.0V, T
AMB
= +25ºC
(unless otherwise specified).
Table 4. Electrical Characteristics
Symbol
Power Supply
V
DD
I
DD
Parameter
Condition
Min
2.70
0.1
110
Typ
Max
5.5
0.5
200
Unit
V
µA
µA
Standby Current
Digital Inputs = V
DD
or GND, T
AMB
= +25ºC
Operating Current
1
I
OP
Includes Non-Volatile Write to Memory
(CMOS write)
DC Performance (Voltage Divider Mode)
N
Resolution
AS1506-10
2
INL
Integral Linearity
AS1506-50 & -100
DNL
TC
R
Differential Non-Linearity
End-to-End Resistance
Temperature Coefficient
Full Scale Error
2
256
±0.5
±0.25
±0.5
±0.25
90
2.5
1.5
1.5
1
0.1
0.1
±1
±0.6
±0.5
±0.5
±0.5
200
120
15
10
50
100
4
2.5
2.5
2
0.7
0.7
±2
±1.5
±1
±1
±1
±1
±0.5
±1
±0.5
Taps
LSB
LSB
ppm/ºC
AS1506-10
AS1506-50 & -100
T
AMB
= 0 to +85ºC
AS1506-10
AS1506-50
AS1506-100
AS1506-10
AS1506-50
AS1506-100
AS1506-10
AS1506-50 & -100 @ 3V
AS1506-50 & -100 @ 5V
AS1506-10
AS1506-50 & -100
V
DD
= 3V
V
DD
= 5V
AS1506-10
AS1506-50
AS1506-100
7.5
37.5
75
LSB
Zero Scale Error
DC Performance (Variable Resistor Mode)
INL
Integral Linearity
3
LSB
LSB
DNL
Differential Non-Linearity
LSB
DC Performance (Resistor Characteristics)
R
W
C
W
R
EE
Wiper Resistance
4
Ω
pF
12.5
62.5
125
kΩ
Wiper Capacitance
End-to-End Resistance
Inputs and Outputs
WIPER Voltage Range
HIGH Voltage Range
LOW Voltage Range
V
IH
V
IL
I
LEAK
C
IN
I
CONT
Digital Input High Voltage
Digital Input Low Voltage
5
GND-
0.3
V
DD
= 3V
V
DD
= 5V
V
DD
= 3V
V
DD
= 5V
2.1
2.4
V
DD
+
0.3
V
V
0.6
0.8
500
560
V
nA
pF
µA
5
Digital Input Leakage Current
Digital Input Capacitance
Continuous DAC current
200
5
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AS1506
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 4. Electrical Characteristics (Continued)
Symbol
Parameter
Condition
AS1506-10
AS1506-50
AS1506-100
AS1506-10
AS1506-50
AS1506-100
T
AMB
= +85ºC
T
AMB
= +25ºC
T
AMB
= +85ºC
Min
Typ
1200
220
120
1100
1600
2200
150
10M
1M
20
Max
Unit
Dynamic Characteristics
Wiper -3dB Bandwidth
6
kHz
t
S
Wiper Settling Time
7
ns
Non-Volatile Memory Reliability
Data Retention
Endurance
t
BUSY
8
8
Years
Write
Cycles
ms
Write Non-Volatile Register
Busy Time
1. The programming current operates only during power-up and non-volatile memory writes.
2. DNL and INL are measured with the potentiometer configured as a voltage-divider with HIGH = V
DD
and LOW =
GND. The wiper terminal is unloaded and measured with a high-input-impedance voltmeter.
3. DNL and INL are measured with the potentiometer configured as a variable resistor. HIGH is unconnected and
LOW = GND. For the 5V condition, the wiper terminal is driven with a source current of 400µA @ 10kΩ, 80µA @
50kΩ, 40µA @ 100kΩ. In 3V conditions, the wiper terminal is driven with a source current of 200µA @ 10kΩ,
40µA @ 50kΩ, 20µA @ 100kΩ.
4. The wiper resistance is measured using the source currents given in Note 3. The number is the worst case
resistance over TAP positions.
5. The device draws higher supply current when the digital inputs are driven with voltages between (V
DD
- 0.5V)
and (GND + 0.5V).
6. Wiper at midscale with a 10pF load (DC measurement) V
DD
= 5V, LOW = GND. An AC source (5V peak to peak
sinus signal) is applied to HIGH and the WIPER output is measured. A 3dB bandwidth occurs when the AC
WIPER/HIGH value is 3dB lower than the DC WIPER/HIGH value.
7. Wiper-settling time is the worst-case 0 to 50% rise-time measured between successive wiper positions. HIGH =
V
DD
, LOW = GND; WIPER is unloaded and measured with a 10pF load.
8. This parameter is not tested but ensured by characterization.
Timing Characteristics
V
DD
= +2.7 to +5.5V, HIGH = V
DD
, LOW = GND, T
AMB
= -40 to +85ºC. Typ values are at V
DD
= +5.0V, T
AMB
= +25ºC
(unless otherwise specified). See
Figure 20 on page 9.
Digital timing data is guaranteed by design and characteriza-
tion, and is not production tested.
Table 5. Timing Characteristics
Symbol
f
SCLK
t
CP
t
CH
t
CL80
t
CSS
t
CSH
t
DS
t
DH
t
CS0
t
CS1
t
CSW
t
BUSY
Parameter
SCLK Frequency
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CSN-Fall to SCLK Rise Setup
SCLK-Rise to CSN-Rise Hold
SDIO to SCLK Setup
SDIO Hold after SCLK
SCLK-Rise to CSN-Fall Delay
CSN-Rise to SCLK-Rise Hold
CSN Pulse-Width High
Write Non-Volatile Register Busy Time
Condition
Min
200
40
40
40
40
10
0
40
40
200
20
Typ
Max
5
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
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