HLX6228
HLX6228
128K x 8 STATIC RAM—Low Power SOI
The 128K x 8 Radiation Hardened Static RAM is a high
performance 131,072 word x 8-bit static random access
memory with industry-standard functionality. It is fabricated
with Honeywell’s radiation hardened technology, and is
designed for use in low voltage systems operating in radiation
environments. The RAM operates over the full military
temperature range and requires only a single 3.3 V ± 0.3V
power supply. The RAM is compatible with JEDEC standard
low voltage CMOS I/O. Power consumption is typically less
than 9 mW/MHz in operation, and less than 2 mW when
deselected. The RAM read operation is fully asynchronous,
with an associated typical access time of 32 ns at 3.3 V.
Honeywell’s
enhanced
SOI
RICMOS™IV
(Radiation
Insensitive CMOS) technology is radiation hardened through
the use of advanced and proprietary design, layout and process hardening techniques. The RICMOS™ IV low power
process is a SIMOX CMOS technology with a 150 Å gate oxide and a minimum drawn feature size of 0.7 µm (0.55 µm
effective gate length—Leff). Additional features include tungsten via plugs, Honeywell’s proprietary SHARP planarization
process and a lightly doped drain (LDD) structure for improved short channel reliability. A 7 transistor (7T) memory cell is
used for superior single event upset hardening, while three layer metal power bussing and the low collection volume
SIMOX substrate provide improved dose rate hardening.
FEATURES
RADIATION
•
Fabricated with RICMOS™ IV Silicon on Insulator
(SOI) 0.7 µm (L
eff
= 0.55 µm)
•
•
•
•
•
•
Total Dose Hardness through 1x10 rad(SiO
2
)
Neutron Hardness through 1x10
14
6
OTHER
•
Read/Write Cycle Times
o
≤
32 ns (-55 to 125°C)
•
•
•
•
•
Typical Operating Power <9 mW/MHz
JEDEC Standard Low Voltage
CMOS Compatible I/O
Single 3.3 V
±
0.3 V Power Supply
Asynchronous Operation
Packaging Options
o
32-Lead Flat Pack (0.820 in. x 0.600 in.)
o
40-Lead Flat Pack (0.775 in. x 0.710 in.)
1
cm-
2
Dynamic and Static Transient Upset Hardness
9
through 1x10 rad(Si)/s
Dose Rate Survivability through <1x10 rad(Si)/s
Soft Error Rate of <1x10
Geosynchronous Orbit
No Latchup
-10
11
upsets/bit-day in
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HLX6228
FUNCTIONAL DIAGRAM
SIGNAL DEFINITIONS
A: 0-16
DQ: 0-7
Address input pins which select a particular eight-bit word within the memory array.
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables
all input buffers except CE. This part must be Read and Write controlled using the NCS pin: it requires that NCS
returns to a high state for at least 5ns whenever there is an address change. This 5ns pulse to high provides the
part with a defined pre-charge pulse duration to ensure that the new address is latched. The part must be
controlled in this fashion to meet the timing specifications defined.
Negative write enable, when at a low level activates a write operation and holds the data output drivers in a high
impedance state. When at a high level NWE allows normal read operation.
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a
low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must be
connected to VSS.
Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
NCS
NWE
NOE
CE
TRUTH TABLE
NCS
L
L
H
X
2
CE
H
H
X
L
NWE
H
L
XX
XX
NOE
L
X
XX
XX
MODE
Read
Write
Deselected
Disabled
DQ
Data Out
Data In
High Z
High Z
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Notes:
X:
VI=VIH or VIL
XX:
VSS≤VI≤VDD
NOE=H: High Z output state
maintained for NCS=X,
CE=X, NWE=X
HLX6228
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature
range after the specified total ionizing radiation dose. All
electrical and timing performance parameters will remain
within specifications after rebound at VDD = 3.6 V and T
=125°C extrapolated to ten years of operation. Total
dose hardness is assured by wafer level testing of
process monitor transistors and RAM product using 10
KeV X-ray and Co60 radiation sources. Transistor gate
threshold shift correlations have been made between 10
5
KeV X-rays applied at a dose rate of 1x10 rad(Si)/min at
T = 25°C and gamma rays (Cobalt 60 source) to ensure
that wafer level X-ray testing is consistent with standard
military radiation test environments.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse, up to the specified transient
dose rate upset specification, when applied under
recommended operating conditions. To ensure validity of
all specified performance parameters before, during, and
after radiation (timing degradation during transient pulse
radiation (timing degradation during transient pulse
radiation is
≤10%),
it is suggested that stiffening
capacitance be placed on or near the package VDD and
VSS, with a maximum inductance between the package
(chip) and stiffening capacitance of 0.7 nH per part. If
there are no operate-through or valid stored data
requirements, typical circuit board mounted de-coupling
capacitors are recommended.
The SRAM is capable of meeting the specified Soft Error
Rate (SER), under recommended operating conditions.
This hardness level is defined by the Adams 90% worst
case cosmic ray environment for geosynchronous orbits.
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under
recommended operating conditions. Fabrication with the
SIMOX substrate material provides oxide isolation
between adjacent PMOS and NMOS transistors and
eliminates any potential SCR latchup structures.
Sufficient transistor body tie connections to the p- and n-
channel substrates are made to ensure no source/drain
snapback occurs.
The SRAM will meet any functional or electrical
specification after exposure to a radiation pulse up to the
transient dose rate survivability specification, when
applied under recommended operating conditions. Note
that the current conducted during the pulse by the RAM
inputs, outputs, and power supply may significantly
exceed the normal operating levels. The application
design must accommodate these effects.
Neutron Radiation
The SRAM will meet any functional or timing
specification after exposure to the specified neutron
fluence under recommended operating or storage
conditions. This assumes equivalent neutron energy of 1
MeV.
Soft Error Rate
RADIATION HARDNESS RATINGS (1)
Parameter
Total Dose
Transient Dose Rate Upset
Transient Dose Rate Survivability
Soft Error Rate (SER)
Neutron Fluence
Limits (2)
≥1x10
≥1x10
≥1x10
<1x10
≥1x10
6
9
Units
rad(Si)
rad(Si)/s
rad(Si)/s
upsets/bit-day
N/cm
2
Test Conditions
T
A
=25°C,
Pulse width
≤20ns,
X-ray, T
A
= 125 C
O
11
Pulse width
≤20
ns, X-ray, T
A
=25°C
T
A
=25°C, Adams 90% worst case environment
1 MeV equivalent energy, Unbiased, T
A
=25°C
-10
14
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Specifications apply to operating conditions (unless otherwise specified) of: VDD=3.0 V to 3.6 V, T
A
=-55°C to 125°C.
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3
HLX6228
ABSOLUTE MAXIMUM RATINGS (1)
Rating
Symbol
VDD
VPIN
TSTORE
TSOLDER
PD
IOUT
VPROT
ΘJC
TJ
Parameter
Supply Voltage Range (2)
Voltage on Any Pin (2)
Storage Temperature (Zero Bias)
Soldering Temperature (5 seconds)
Maximum Package Power Dissipation (3)
DC or Average Output Current
ESD Input Protection Voltage (4)
Thermal Resistance (Jct-toCase)
Junction Temperature
32 FP
40 FP
Min
-0.5
-0.5
-65
Max
6.5
VDD +0.5
150
270
2.5
25
2
2
175
Units
V
V
°C
°C
W
mA
V
°C / W
°C / W
°C
2000
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these
levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this
specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
TA
VPIN
VDD Ramp
Time
Parameter
Supply Voltage (referenced to VSS)
Ambient Temperature
Voltage on Any Pin (referenced to VSS)
Supply Voltage Ramp Time
Min
3.0
-55
-0.3
Description
Typ
3.3
25
Max
3.6
125
VDD+0.3
50
Units
V
°C
V
ms
CAPACITANCE (1)
Symbol
CI
CO
Parameter
Input Capacitance
Output Capacitance
Typical
Worst Case
Min
Max
7
9
Units
pF
pF
Test Conditions
VI=VDD or VSS, f=1 MHz
VIO=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial design characterization only.
DATA RETENTION CHARACTERISTICS
Symbol
VDR
IDR
Parameter
Data Retention Voltage
Data Retention Current
Typical (1)
Worst Case (2)
Min
Max
2.5
700
Units
V
μA
Test Conditions
NCS=VDR, VI=VDR or VSS
NCS=VDD=VDR, VI=VDD or VSS
(1) Typical operating conditions: TA= 25°C, pre-radiation.
(2) Worst case operating conditions: TA= -55°C to +125°C, post total dose at 25°C.
4
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HLX6228
DC ELECTRICAL CHARACTERISTICS
Symbol
IDDSB1
IDDSBMF
IDDOPW
IDDOPR
II
IOZ
VIL
VIH
VOL
VOH
Parameter
Static Supply Current
Standby Supply Current –
Deselected
Dynamic Supply Current – Selected
(Write)
Typical
(1)
Worst Case (2)
Min
Max
700
700
3.2
2.2
-5
-10
5
10
0.27xV
DD
.725xV
DD
0.4
2.7
Units
µA
µA
mA
mA
μA
μA
V
V
V
V
Test Conditions
VIH=VDD, IO=0
VIL=VSS, Inputs Stable
NCS=VDD, CE=VSS, IO=0,
f=40 MHZ
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
F=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
VSS <VI <VDD
VSS <VI<VDD, Output = high
Z
March Pattern, VDD = 3.0V
March Pattern, VDD = 3.6V
VDD=3.0V, IOL = 8 mA
VDD=3.0V, IOL = -4 mA
Dynamic Supply Current – Selected
(Read)
Input Leakage Current
Output Leakage Current
Low-Level Input Voltage
High-Level Input Voltage
Low-Level Output Voltage
High-Level Output Voltage
(1) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.
(2) Worst case operating conditions: VDD=3.0 V to 3.6 V, -55°C to +125°C, post total dose at 25°C.
(3) All inputs switching. DC average current.
SIGNAL INTEGRITY AND SIGNAL CONNECTIONS
It is important that input signal transitions (between VIL
and VIH levels) that produce asynchronous behavior
(i.e., Address, Read/Write, Chip Select/Enable) have
good signal integrity (free of noise, glitches, ringing or
discontinuities from impedance mismatch reflections or
driver changes) and have rising and falling edges of
≤10ns. Input signal transitions with poor signal integrity,
slow state changes (>10ns) or where the driver changes
between VIL and VIH levels, when the chip is enabled
and selected, can interfere with intended read or write
operations. Note: Some examples of “driver change”
include changing from a floating or weakly driven (e.g.,
weak pull-up or pull-down) input state to an active driver
defined input state or changing between devices driving
the signal input.
In addition, input signals should not be left floating
unless the chip is disabled or deselected.
TESTER EQUIVALENT LOAD CIRCUIT
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