Datas heet
AS1339
6 5 0 m A R F St e p - D o w n D C - D C f o r PA, w i t h t w o L D O s
1 General Description
The AS1339 is a high-frequency step-down converter
optimized for dynamically powering the power amplifier
(PA) in WCDMA or NCDMA handsets. The device uses
a 110mΩ typical bypass FET to power the PA directly
from the battery during high-power transmission. The IC
integrates two 10mA low-noise, low-dropout regulators
(LDOs) for PA biasing.
With a switching frequency of 2MHz, the device allows
optimization for smallest solution size or highest
efficiency. The AS1339 supports fast switching using
small ceramic 10μF input and 4.7µF output capacitors to
maintain low ripple voltage.
The AS1339 uses an analog input driven by an external
DAC to control the output voltage linearly for continuous
PA power adjustment. The gain from REFIN to OUT is
2.5V/V. At high-duty cycle, the device automatically
switches to a bypass mode, connecting the input to the
output through a low-impedance MOSFET. The LDOs
are designed for low-noise operation, wherein each LDO
in the device is individually enabled through its own logic
control interface. The device is available in a 16-pin
WLP (2x2mm) package.
2 Key Features
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Fixed Switching Frequency: 2MHz
PA Step-Down Converter
Low Dropout Voltage
Low Output-Voltage Ripple
Dynamic Output Voltage Control (0.8V to 3.75V)
30µs Settling Time for 0.8V to 3.4V Output Voltage
Change
650mA Output Drive Capability
Two 10mA Low-Noise LDOs
Low Shutdown Current
Supply Voltage Range: 2.7V to 5.5V
Thermal Shutdown
16-pin WLP (2x2mm) package
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3 Applications
The AS1339 is ideal for WCDMA/NCDMA cellular
handsets, Wireless PDAs, and Smartphones.
Figure 1. AS1339 - Typical Operating Circuit
V
IN
2.7V to 5.5V
10µF
V
PA
0.8V to 3.75V
IN1A
PAA
PAB
IN1B
LX
2.2µH
4.7µF
PGND
NC
Analog Control
REFIN
PA ON/OFF
LDO1 ON/OFF
LDO2 ON/OFF
NC
V
IN
2.7V to 5.5V
1µF
PA_EN
EN1
AS1339
LDO1
2.85V
0.1µF
EN2
TEST
IN2
AGND
LDO2
2.85V
0.1µF
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AS1339
Datasheet - P i n o u t
4 Pinout
Figure 2. Pin Assignments (Top View)
NC
A1
LDO2
B1
IN2
C1
LDO1
D1
AGND
A2
PA_EN
B2
TEST
C2
EN1
D2
REFIN
A3
EN2
B3
IN1B
C3
PAB
D3
PGND
A4
LX
B4
IN1A
C4
PAA
D4
Pin Description
Table 1. Pin Description
Pin Name
NC
AGND
REFIN
PGND
LDO2
Pin Number
A1
A2
A3
A4
B1
Description
Not Connected.
Free, high impedance for normal operation. Used for
internal test purpose.
Low-Noise Analog Ground
DAC-Controlled Input.
Reference voltage for buck converter. The output of
the PA step-down converter is regulated to 2.5 x V
REFIN
. Bypass mode is
enabled when V
IN
≤
2.69V x V
REFIN
.
Power Ground
for PA Step-Down Converter
10mA LDO Regulator 2 Output.
Connect LDO2 with a 0.1μF ceramic
capacitor as close as possible to LDO2 and AGND. LDO2 is internally pulled
down through a 100Ω resistor when this regulator is disabled.
PA Step-Down Converter Enable Input.
For normal operation, connect to
logic-high. For shutdown mode, connect to logic-low. The pin is internally
pulled down through a 110kΩ resistor.
Enable Input for LDO2.
For normal operation, connect to logic-high. For
shutdown mode, connect to logic-low. The pin is internally pulled down
through a 110kΩ resistor.
Inductor Connection.
Connect an inductor from LX to the output of the PA
step-down converter.
PA_EN
B2
EN2
LX
B3
B4
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AS1339
Datasheet - P i n o u t
Table 1. Pin Description
Pin Name
IN2
Pin Number
C1
Description
Supply Voltage Input for LDO1 and LDO2.
Connect IN2 to a battery or
supply voltage from 2.7V to 5.5V. Decouple IN2 with a 1μF ceramic
capacitor as close as possible to IN2 and AGND. Connect IN2 to the same
source as IN1A and IN1B.
NC.
Used for internal test purpose. The pin is internally pulled down with a
110kΩ resistor.
Supply Voltage Input for PA Step-Down Converter.
Connect IN1A/B to a
battery or supply voltage from 2.7V to 5.5V. Decouple IN1A/B with a 10μF
ceramic capacitor as close as possible to IN1A/B, and PGND. IN1A and
IN1B are internally connected together. Connect IN1A/B to the same source
as IN2.
10mA LDO Regulator 1 Output.
Decouple LDO1 with a 0.1μF ceramic
capacitor as close as possible to LDO1 and AGND. LDO1 is internally pulled
down through a 100Ω resistor when this regulator is disabled.
Enable Input for LDO1.
For normal operation, connect to logic-high. For
shutdown mode, connect to logic-low. The pin is internally pulled down
through a 110kΩ resistor.
PA Connection for Bypass Mode.
Internally connected to IN1A/B using
the internal bypass MOSFET during bypass mode. Connect PAA/B with a
4.7μF ceramic capacitor as close as possible to PAA/B and PGND.
TEST
C2
IN1B, IN1A
C3, C4
LDO1
D1
EN1
D2
PAB, PAA
D3, D4
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AS1339
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in
Table 2
may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in
Electrical Character-
istics on page 5
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 2. Absolute Maximum Ratings
Parameter
IN1A, IN1B, IN2 to AGND
PAA, PAB, PA_EN, TEST, REFIN,
NC to AGND
LDO1, LDO2, EN1, EN2 to AGND
REFIN Common-Mode Range
IN2 to IN1B/IN1A
PGND to AGND
LX Current
Bypass Current
Human Body Model
Storage Temperature Range
-65
1
+150
Min
-0.3
-0.3
-0.3
0
-0.3
-0.3
Max
+7
V
IN1A
/
V
IN1B
+
0.3
V
IN2
+
0.3
V
IN
+0.3
+0.3
0.8
1.6
Units
V
V
V
V
V
V
A
RMS
A
RMS
kV
ºC
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020D “Moisture/Reflow
Sensitivity Classification for Non-Hermetic Solid
State Surface Mount Devices”.
T
A
= +65ºC; derate 12.5mW/ºC above +65ºC
HBM MIL-Std. 883E 3015.7
methods
Comments
Package Body Temperature
+260
ºC
Continuous Power Dissipation
P
D-MAX
Junction Temperature (T
J
) Range
-40
0.75
+125
W
ºC
Ambient Temperature (T
A
) Range
-40
+85
ºC
In applications where high power dissipation
and/or poor package thermal resistance is
present, the maximum ambient temperature
may have to be derated.
Maximum ambient temperature (T
A-MAX
) is
dependent on the maximum operating junction
temperature (T
J-MAX-OP
= 125ºC), the maximum
power dissipation
of the device in the application (P
D-MAX
), and the
junction-to ambient thermal resistance of the
part/package in the application (θ
JA
), as given by
the following
equation: T
A-MAX
= T
J-MAX-OP
– (θ
JA
× P
D-MAX
).
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AS1339
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
V
IN1A
= V
IN1B
= V
IN2
= V
PA_EN
= V
EN1
= V
EN2
= 3.6V, T
A
= -40ºC to +85ºC. Typical values are at T
A
=+25ºC, (unless
otherwise specified), for external components refer to
Table 5 on page 7.
Table 3. Electrical Characteristics
Symbol
Input Supply
V
IN
I
SHDN
I
Q
Input Voltage Range
Shutdown Supply Current
DC-DC No-Load Supply
Current
Load Current
Output Voltage Range
V
OUT
Output Voltage
PWM Mode
V
REFIN
= 0.32V,
V
IN
= 3.9V
V
REFIN
= 0.84V,
V
IN
= 3.9V
V
REFIN
= 1.36V,
V
IN
= 3.9V
Thermal Protection
Thermal Shutdown
Logic Control
PA_EN, EN1, EN2, Logic-
Input High Voltage
PA_EN, EN1, EN2, Logic-
Input Low Voltage
Logic-Input Current
(PA_EN, EN1, EN2)
REFIN
REFIN Operating
Common-Mode Range
REFIN gain V
OUT
/V
REFIN
REFIN Current
LX
R
DSONP
Pin-Pin Resistance for PFET
R
DSONN
Pin-Pin Resistance for NFET
PFET Leakage Current
NFET Leakage Current
PFET Peak Current Limit
I
SW
= 200mA; T
A
= +25°C
I
SW
= 200mA
I
SW
= -200mA; T
A
= +25°C
I
SW
= -200mA
V
IN
= 5.5V, V
LX
= 0V
V
IN
= V
LX
= 5.5V
V
LX
= 0V
0.1
0.1
1100
230
110
200
230
415
485
3
3
mΩ
mΩ
µA
µA
mA
2
Parameter
Condition
Min
2.7
Typ
Max
5.5
Unit
V
µA
mA
V
PA_EN
= V
EN1
= V
EN2
= 0V
1
0.1
4.5
1
6
V
EN1
= V
EN2
= 0V, I
LOAD(DCDC)
= 0mA,
switching,
V
IN
= 4.5V, V
OUT
= 3.4V
DCDC Output Voltage
I
LOAD
650
0.8
0.75
2.05
3.319
0.8
2.1
3.4
+140
3.85
0.85
2.15
3.481
mA
V
V
V
V
ºC
T
A
rising, 10ºC typical hysteresis
2.7V
≤
V
IN
≤
5.5V
2.7V
≤
V
IN
≤
5.5V
V
IL
= 0V
V
IH
=
V
IN
= 5.5V
1.4
0.5
-1
50
+1
75
V
V
µA
µA
0.32
V
REFIN
= 0.32V
V
REFIN
= 0.84V, 1.36V
V
REFIN
=
V
IN
= 5.5V
2.35
2.44
-1
2.50
2.50
1.5
2.65
2.56
+1
V
V/V
V/V
µA
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