SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
•
•
•
•
•
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
Choice of True or Inverting Data Paths
Choice of 3-State or Open-Collector
Outputs
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
DEVICE
OUTPUT
3 state
3 state
LOGIC
True
Inverting
SN54ALS646, SN54ALS648, SN54AS646 . . . JT PACKAGE
SN74ALS646A, SN74ALS648A, SN74AS646,
SN74AS648 . . . DW OR NT PACKAGE
(TOP VIEW)
SN54ALS646, SN74ALS646A,
′AS646
SN54ALS648, SN74ALS648A, SN74AS648
description
These devices consist of bus-transceiver circuits
with 3-state or open-collector outputs, D-type
flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Data on the A or B bus is clocked into the registers
on the low-to-high transition of the appropriate
clock (CLKAB or CLKBA) input. Figure 1
illustrates the four fundamental bus-management
functions that can be performed with the octal bus
transceivers and registers.
Output-enable (OE) and direction-control (DIR)
inputs control the transceiver functions. In the
transceiver mode, data present at the high-
impedance port may be stored in either or both
registers.
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
SN54ALS646, SN54ALS648, SN54AS646 . . . FK PACKAGE
(TOP VIEW)
DIR
SAB
CLKAB
NC
V
CC
CLKBA
SBA
A1
A2
A3
NC
A4
A5
A6
4
5
6
7
8
9
10
3
2 1 28 27 26
25
24
23
22
21
20
19
11
12 13 14 15 16 17 18
OE
B1
B2
NC
B3
B4
B5
The select-control (SAB and SBA) inputs can
NC – No internal connection
multiplex stored and real-time (transparent mode)
data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during
the transition between stored and real-time data. DIR determines which bus receives data when OE is low. In
the isolation mode (OE high), A data may be stored in one register and /or B data may be stored in the other
register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
The -1 version of the SN74ALS646A is identical to the standard version, except that the recommended
maximum I
OL
in the -1 version is increased to 48 mA. There are no -1 versions of the SN54ALS646,
SN54ALS648, or SN74ALS648A.
The SN54ALS646, SN54ALS648, and SN54AS646 are characterized for operation over the full military
temperature range of – 55°C to 125°C. The SN74ALS646A, SN74ALS648A, SN74AS646, and SN74AS648 are
characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
A7
A8
GND
NC
B8
B7
B6
Copyright
©
1995, Texas Instruments Incorporated
1
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
Function Tables
SN54ALS646, SN54AS646, SN74ALS646A, SN74AS646
INPUTS
OE
X
X
H
H
L
L
L
L
DIR
X
X
X
X
L
L
H
H
CLKAB
↑
X
↑
H or L
X
X
X
H or L
CLKBA
X
↑
↑
H or L
X
H or L
X
X
SAB
X
X
X
X
X
X
L
H
SBA
X
X
X
X
L
H
X
X
A1– A8
Input
Unspecified†
Input
Input disabled
Output
Output
Input
Input
DATA I/O
B1– B8
Unspecified†
Input
Input
Input disabled
Input
Input
Output
Output
OPERATION OR FUNCTION
Store A, B unspecified†
Store B, A unspecified†
Store A and B data
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
† The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
SN54ALS648, SN74ALS648A, SN74AS648
INPUTS
OE
X
X
H
H
L
L
L
L
DIR
X
X
X
X
L
L
H
H
CLKAB
↑
X
↑
H or L
X
X
X
H or L
CLKBA
X
↑
↑
H or L
X
H or L
X
X
SAB
X
X
X
X
X
X
L
H
SBA
X
X
X
X
L
H
X
X
A1– A8
Input
Unspecified†
Input
Input disabled
Output
Output
Input
Input
DATA I/O
B1– B8
Unspecified†
Input
Input
Input disabled
Input
Input
Output
Output
OPERATION OR FUNCTION
Store A, B unspecified†
Store B, A unspecified†
Store A and B data
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
† The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
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