14-Bit, 10 MSPS Monolithic A/D
Converter with LPT ASIC
9240LP
Memory
F
EATURES
:
• R
AD
-P
AK
® radiation-hardened against natural space radia-
tion
• Low power dissipation: 285 mW
• Single 5 V supply
• Integral nonlinearity error: 2.5 LSB
• Differential nonlinearity error: 0.6 LSB
• Input referred noise: 0.36 LSB
• Complete: On-chip sample-and-hold amplifier and voltage
reference
• Signal-to-noise and distortion ration: 77.5 dB
• Spurious-free dynamic range: 90 dB
• Out-of-range indicator
• Straight binary output data
• Total dose hardened to 100 Krads (Si), dependent on orbit
and mission duration
• Single Event Latchup (SEL) protected
D
ESCRIPTION
:
Maxwell Technologies’ 9240LP is a 14-bit, analog-to-digital
converter that operates at a 10 MSPS rate. Manufactured with
a high speed CMOS process, this monolithic ADC contains an
on-chip, high performance, low noise, sample-and-hold ampli-
fier and programmable voltage reference.
The 9240LP offers single supply operation and dissipates only
480 mW with a 5 volt supply. This device provides no missing
codes and excellent temperature drift performance over the
full operating temperature range.
The 9240LP utilizes Maxwell’s LPT™ Latchup Protection Cir-
cuit.
Maxwell Technologies' patented R
AD
-P
AK
® packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
AD
-P
AK
provides protection to 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
03.08.02 Rev 4
(858) 503-3300- Fax: (858) 503-3301- www.maxwell.com
All data sheets are subject to change without notice
1
©2002 Maxwell Technologies
All rights reserved.
14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC
T
ABLE
1. 9240LP P
IN
D
ESCRIPTION
P
IN
N
UMBER
1
2, 29
3
4, 28
5
6
7
8
9
N
AME
DVSS
AVSS
DVDD
AVDD
NC
DRVDD
CLK
LPTSTATUS
LPTBIT
D
ESCRIPTION
Digital Ground
Analog Ground
5V Digital Supply
5V Analog Supply
No Connect
Digital Output Driver Supply
Clock Input Pin
A 0 to 5V pulse is output during the decision
time and protect time. Normally low.
The LPT circuit will crowbar the power supplies
to the 9240LP for as long as a logic high is
applied. Used to verify operation of the LPT.
Normally a logical low or ground is applied to
this input.
No Connect
Least Significant Data Bit (LSB)
Data Output Bits
Most Significant Data Bits (MSB)
Out of Range
No Connect
Reference Select
Reference I/O
Reference Common
No Connect
Power/Speed Programming
Noise Reduction Pin
Noise Reduction Pin
Common-Mod Level (Midsupply)
Protected Reference I/O
Analog Input Pin (+)
Analog Input Pin (-)
Protected 5V Digital Supply
Protected 5V Analog Supply
9240LP
Memory
10
11
12-23
24
25
26, 27, 30
31
32
33
34, 38
35
36
37
39
40
41
42
43
44
NC
BIT 14
BIT 13-BIT 2
BIT 1
OTR
NC
SENSE
VREF
REFCOM
NC
BIAS
1
CAPB
CAPT
CML
LPTVREF
VINA
VINB
LPTDVDD
LPTAVDD
1. See Speed/Power programmability section.
03.08.02 Rev 4
All data sheets are subject to change without notice
2
©2002 Maxwell Technologies
All rights reserved.
14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC
T
ABLE
2. 9240LP A
BSOLUTE
M
AXIMUM
R
ATINGS 1
P
ARAMETER
+5 V Analog Supply
+5 V Digital Supply
Analog Ground
+5 V Analog Supply
Digital Output Driver Supply
Digital Output Driver Ground
Reference Common
Clock Input Pin
Digital Outputs
Analog Inputs
Reference I/O
Reference Select
Noise Reduction Pins
Power/Speed Programming
Junction Temperature
Operating Temperature
Storage Temperature
Lead Temperature (10 sec)
S
YMBOL
AVDD
DVDD
AVSS
AVDD
DRVDD
DRVSS
REFCOM
CLK
Data Out Bits
VINA, VINB
VREF
Sense
CAPB, CAPT
BIAS
T
J
T
A
T
STG
T
L
W
ITH
R
ESPECT
T
O
AVSS
DVSS
DVSS
DVDD
DRVSS
AVSS
AVSS
AVSS
DRVSS
AVSS
AVSS
AVSS
AVSS
AVSS
M
IN
-0.3
-0.3
-0.3
-6.5
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
--
-55
-65
--
M
AX
6.5
6.5
0.3
6.5
6.5
0.3
0.3
9240LP
U
NIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°
C
AVDD + 0.3
DRVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + -.3
150
125
150
300
Memory
°C
°
C
°
C
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any other conditions above those indicated in the operational sec-
tions of this specification are not implied. Exposure to absolute maximum ratings for extended periods may effect device reli-
ability.
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
I
CC
V
ARIATION
±10%
OF SPECIFIED VALUE IN
T
ABLE
4
03.08.02 Rev 4
All data sheets are subject to change without notice
3
©2002 Maxwell Technologies
All rights reserved.
14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC
T
ABLE
4. 9240LP DC S
PECIFICATIONS
S
UBGROUPS
1
9, 10, 11
M
IN
14
10
--
--
1, 2, 3
1, 2, 3
1, 2, 3
1
1
--
1
1, 2, 3
--
--
--
1, 2, 3
--
2
--
0
--
--
--
--
--
--
--
--
1, 2, 3
--
3.0
20.0
5.0
--
--
--
--
--
16
1
--
2.5
--
5
--
5
--
--
--
0.1
--
5
--
AVDD
--
--
±14
--
±35
--
10.0
--
--3.0
--
--
--
--
--3
--1.5
--0.75
T
YP1
--
--
0.9
0.36
±2.5
±0.6
±2.5
±0.7
--
--
--
9240LP
(AVDD = 5V, DVDD = 5V, DRVDD = 5V, f
SAMPLE
= 10 MSPS, R
BIAS
= 2
K
Ω
, VREF = 2.5V, VINB = 2.5V, T
A
= -55
TO
+125°C,
UNLESS
OTHERWISE SPECIFIED
)
P
ARAMETER
RESOLUTION
MAX CONVERSION RATE
MAX REFERRED NOISE
1
VREF = 1 V
VREF = 2.5V
ACCURACY
2
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL
3
DNL
3
No Missing Codes
Zero Error (@ 25 °C)
Gain Error (@ 25 °C)
4,1
Gain Error (@ 25 °C)
5
TEMPERATURE DRIFT
Zero Error
Gain Error
4
Gain Error
5
POWER SUPPLY REJECTION
ANALOG INPUT
Input Span (with VREF = 1.0 V)
1
(with VREF = 2.5 V)
Input (VINA or VINB) Range
Input Capacitance
1
INTERNAL VOLTAGE REFERENCE
1
Output Voltage (1V mode)
Output Voltage Tolerance (1 V Mode)
Output Voltage (2.5 V Mode)
Output Voltage Tolerance (2.5 V Mode)
Load Regulation V
REF6
Load Regulation LPTV
REF1, 6, 7
REFERENCE INPUT RESISTANCE
M
AX
--
--
--
--
+3.0
±1.0
--
--
14
+3
1.5
0.75
U
NIT
Bits
MHz
LSB rms
LSB rms
LSB
LSB
LSB
LSB
Bits Guaranteed
% FSR
% FSR
% FSR
ppm/°C
ppm/°C
ppm/°C
% FSR
V p-p
V p-p
V
V
pF
Volts
mV
Volts
mV
mV
mV
k
Ω
Memory
1, 2, 3
--
--
03.08.02 Rev 4
All data sheets are subject to change without notice
4
©2002 Maxwell Technologies
All rights reserved.
14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC
T
ABLE
4. 9240LP DC S
PECIFICATIONS
S
UBGROUPS
1, 2, 3
--
--
--
--
--
--
--
--
--
--
--
--
--
8
--
--
105
105
10
70
75
±15
28
±5
15
--
4.2
14.5
--
--
--
--
--
--
--
--
M
IN
T
YP1
9240LP
(AVDD = 5V, DVDD = 5V, DRVDD = 5V, f
SAMPLE
= 10 MSPS, R
BIAS
= 2
K
Ω
, VREF = 2.5V, VINB = 2.5V, T
A
= -55
TO
+125°C,
UNLESS
OTHERWISE SPECIFIED
)
P
ARAMETER
LPT ASIC
RDS ON
- V
REF
- AVDD
- DVDD
- V
IN
A
- V
IN
B
LATCHUP PROTECTION
- Decision Time
- Protect Time
- AVDD Trip Current
- AVDD Trip Current Tolerance
- DVDD Trip Current
- DVDD Trip Current Tolerance
POWER SUPPLIES
Supply Voltages
- AVDD
- DVDD
- DRVDD
Supply Current
- IAVDD
- IDVDD
POWER CONSUMPTION
1. Guaranteed by design.
2. Tested using external VREF with servo control
3. VREF = 1V.
4. Including internal reference.
5. Excluding internal reference.
6. Load regulation with 1 mA load current.
7. LPTV
REF
should not be capacitively loaded above 0.1 µF.
1, 2, 3
1, 2, 3
1, 2, 3
M
AX
U
NIT
ohm
ohm
ohm
ohm
ohm
ohm
µs
µs
mA
mA
mA
mA
Memory
--
--
--
--
--
5
5
5
48
11
295
--
--
--
55
16
355
V (±5% AVDD Operating)
V (±5% DVDD Operating)
V (±5% DRVDD Operating)
mA
mA
mW
03.08.02 Rev 4
All data sheets are subject to change without notice
5
©2002 Maxwell Technologies
All rights reserved.
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