formance characteristics allow its use in the most
critical instrumentation applications.
Bias current, noise, voltage offset, drift, open-loop
gain, common-mode rejection and power supply re-
jection are superior to BIFET and CMOS amplifiers.
Difet
fabrication achieves extremely low input bias
currents without compromising input voltage noise
performance. Low input bias current is maintained
over a wide input common-mode voltage range with
unique cascode circuitry. This cascode design also
allows high precision input specifications and reduced
susceptibility to flicker noise. Laser trimming of thin-
film resistors gives very low offset and drift.
Compared to the popular OPA111, the OPA124 gives
comparable performance and is available in an 8-pin
PDIP and 8-pin SOIC package.
BIFET
®
National Semiconductor Corp.,
Difet
®
Burr-Brown Corp.
+V
CC
7
8
–In
2
+In
3
Noise-Free Cascode
(2)
Output
6
Trim
(1)
1
Trim
(1)
5
2kΩ
2kΩ
–V
CC
4
10kΩ
2kΩ
2kΩ
10kΩ
OPA124 Simplified Circuit
NOTES: (1) Omitted on SOIC. (2) Patented.
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
NOTES: (1) Offset voltage, offset current, and bias current are measured with the units fully warmed up. For performance at other temperatures see Typical Performance
Curves. (2) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive.
(3) For performance at other temperatures see Typical Performance Curves. (4) Sample tested, 98% confidence. (5) Guaranteed by design.
±10
92
86
106
V
CM
= 0VDC
T
A
= T
MIN
to T
MAX
V
CC
=
±10V
to
±18V
T
A
= T
MIN
to T
MAX
V
CM
= 0VDC
V
CM
= 0VDC
CONDITION
MIN
TYP
40
15
8
6
0.7
1.6
9.5
0.5
±200
±4
110
100
±1
±1
10
13
|| 1
10
14
|| 3
±11
110
100
125
1.5
32
1.6
0.0003
6
10
5
±11
±5.5
±12
±10
100
1000
40
±15
2.5
–25
–65
90
100
T
T
T
94
T
T
MAX
80
40
15
8
1.2
3.3
15
0.8
±800
±7.5
90
86
±5
±5
MIN
OPA124UA, PA
TYP
T
T
T
T
T
T
T
T
±150
±2
T
T
±0.5
±0.5
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
±18
3.5
+85
+125
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
100
90
120
MAX
T
T
T
T
T
T
T
T
±500
±4
100
90
±2
±1
MIN
OPA124PB
TYP
T
T
T
T
T
T
T
T
±100
±1
T
T
±0.35
±0.25
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
MAX
T
T
T
T
T
T
T
T
±250
±2
UNITS
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µVrms
µVp-p
fAp-p
fA/√Hz
µV
µV/°C
dB
dB
pA
pA
Ω
|| pF
Ω
|| pF
V
dB
dB
dB
MHz
kHz
V/µs
%
µs
µs
µs
V
mA
Ω
pF
mA
VDC
VDC
mA
°C
°C
°C/W
°C/W
88
84
±1
±0.5
V
IN
=
±10VDC
T
A
= T
MIN
to T
MAX
R
L
≥
2kΩ
20Vp-p, R
L
= 2kΩ
V
O
=
±10V,
R
L
= 2kΩ
Gain = –1, R
L
= 2kΩ
10V Step
Gain = –1
R
L
= 2kΩ
V
O
=
±10VDC
DC, Open Loop
Gain = +1
16
1
T
T
T
T
10
T
T
±5
I
O
= 0mADC
T
MIN
and T
MAX
®
OPA124
2
CONNECTION DIAGRAMS
Top View
DIP
Top View
SOIC
Offset Trim
–In
+In
–V
S
1
2
3
4
8
7
6
5
Substrate
+V
S
Output
Offset Trim
NC
–In
+In
–V
S
1
2
3
4
NC = No Connect
8
7
6
5
Substrate
+V
S
Output
NC
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING NUMBER
(1)
182
006
182
006
006
TEMPERATURE
RANGE
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
BIAS
CURRENT
pA, max
5
5
2
2
1
OFFSET
DRIFT
µ
V/
°
C, max
7.5
7.5
4
4
2
PRODUCT
OPA124U
OPA124P
OPA124UA
OPA124PA
OPA124PB
PACKAGE
8-Lead SOIC
8-Pin Plastic DIP
8-Lead SOIC
8-Pin Plastic DIP
8-Pin Plastic DIP
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
Junction Temperature .................................................................... +175°C
NOTES: (1) Stresses above these ratings may cause permanent damage.
(2) Packages must be derated based on
θ
JA
= 90°C/W for PDIP and 100°C/W
for SOIC. (3) For supply voltages less than
±18VDC,
the absolute maximum
input voltage is equal to +18V > V
IN
> –V
CC
– 6V. See Figure 2. (4) Short circuit
may be to power supply common only. Rating applies to +25°C ambient.
Observe dissipation limit and T
J
.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
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