HCTL-2000, HCTL-2016, HCTL-2020
Quadrature Decoder/Counter Interface ICs
Data Sheet
Description
The HCTL-2000, 2016, 2020 are CMOS ICs that perform the
quadrature decoder, counter, and bus interface function.
The HCTL-20XX family is designed to improve system per-
formance in digital closed loop motion control systems
and digital data input systems. It does this by shifting
time intensive quadrature decoder functions to a cost
effective hardware solution. The entire HCTL-20XX family
consists of a 4x quadrature decoder, a binary up/down
state counter, and an 8-bit bus interface.
Features
Interfaces encoder to microprocessor
14 MHz clock operation
Full 4X decode
High noise immunity: Schmitt Trigger inputs digital
noise filter
12 or 16-bit binary up/down counter
Latched outputs
8-Bit tristate interface
8, 12, or 16-bit operating modes
Quadrature decoder output signals, up/down and
count
Cascade output signals, up/down and count
DIGITAL MOTION ENCODING
Substantially reduced system software
Applications
Interface quadrature incremental encoders to micro-
processors
Interface digital potentiometers to digital data input
buses
Note: Avago Technologies encoders are not recommended for use in
safety critical applications. Eg. ABS braking systems, power steering, life
support systems and critical care medical equipment. Please contact
sales representative if more clarification is needed.
PINOUT A
PINOUT B
Devices
Part Number
HCTL-2000
HCTL-2016
HCTL-2020
Description
12-bit counter. 14 MHz clock operation.
All features of the HCTL-2000. 16-bit counter.
All features of the HCTL-2016. Quadrature decoder output signals. Cascade output signals.
Package Drawing
A
A
B
ESD WARNING:
Standard CMOS handling precautions should be observed with the HCTL-20XX family ICs.
The use of Schmitt-triggered CMOS inputs and input noise
filters allows reliable operation in noisy environments. The
HCTL- 2000 contains a 12-bit counter. The HCTL-2016 and
2020 contain a 16-bit counter. The HCTL-2020 also contains
quadrature decoder output signals and cascade signals
for use with many standard counter ICs. The HCTL-20XX
family provides LSTTL compatible tristate output buffers.
Operation is specified for a temperature range from -40 to
+85° C at clock frequencies up to 14 MHz.
Package Dimensions
Operating Characteristics
Table 1. Absolute Maximum Ratings
(All voltages below are referenced to V
SS
)
Parameter
DC Supply Voltage
Input Voltage
Storage Temperature
Operating Temperature
Symbol
V
DD
V
IN
T
S
T
A[1]
Limits
-0.3 to +5.5
-0.3 to V
DD
+0.3
-40 to +125
-40 to +85
Units
V
V
°C
°C
Table 2. Recommended Operating Conditions
Parameter
DC Supply Voltage
Ambient Temperature
Symbol
V
DD
T
A[1]
Limits
+4.5 to +5.5
-40 to +85
Units
V
°C
2
Table 3. DC Characteristics
V
DD
= 5 V ± 5%; T
A
= -40 to 85° C
Parameter
Low-Level Input Voltage
High-Level Input Voltage
Schmitt-Trigger Positive-Going Threshold
Schmitt-Trigger Negative-Going Threshold
Schmitt-Trigger Hysteresis
Input Current
High-Level Output Voltage
Low-Level Output Voltage
High-Z Output Leakage Current
Quiescent Supply Current
Input Capacitance
Output Capacitance
Symbol
V
IL[2]
V
IH[2]
V
T
+
V
T
-
V
H
I
IN
V
OH[2]
V
OL[2]
I
OZ
I
DD
C
IN
C
OUT
Condition
Min.
3.5
Typ.
Max.
1.5
Unit
V
V
V
V
V
3.5
1.0
1.0
V
IN
= V
SS
or V
DD
I
OH
-1.6 mA
I
OL
= +4.8 mA
V
O
= V
SS
or V
DD
V
IN
= V
SS
or V
DD
, V
O
= HiZ
Any Input
[3]
Any Outpu
t[3]
-10
-10
2.4
1.5
2.0
1
4.5
0.2
1
1
5
6
4.0
+10
0.4
+10
5
A
V
V
A
A
pF
pF
Notes:
1. Free air.
2. In general, for any VDD between the allowable limits (+4.5 V to +5.5 V), V
IL
= 0.3 V
DD
and V
IH
= 0.7 V
DD
; typical values are V
OH
= V
DD
- 0.5 V @ I
OH
=
-40
A
and V
OL
= V
SS
+ 0.2 V @ I
OL
= 1.6 mA.
3. Including package capacitance.
Figure 1. Reset Waveform.
Figure 2. Waveform for Positive Clock Related Delays.
3
Functional Pin Description
Table 4. Functional Pin Descriptions
Symbol
V
DD
V
SS
CLK
CHA
CHB
RST
Pin
2000/2016
16
8
2
7
6
5
Pin
2020
20
10
2
9
8
7
Description
Power Supply
Ground
CLK is a Schmitt-trigger input for the external clock signal.
CHA and CHB are Schmitt-trigger inputs which accept the outputs from a quadrature
encoded source, such as incremental optical shaft encoder. Two channels, A and B,
nominally 90 degrees out of phase, are required.
This active low Schmitt-trigger input clears the internal position counter and the
position latch. It also resets the inhibit logic. RST is asynchronous with respect to any
other input signals.
This CMOS active low input enables the tri-state output buffers. The OE and SEL
inputs are sampled by the internal inhibit logic on the falling edge of the clock to
control the loading of the internal position data latch.
This CMOS input directly controls which data byte from the position latch is enabled
into the 8-bit tri-state output buffer. As in OE above, SEL also controls the internal
inhibit logic.
OE
4
4
SEL
3
3
SEL
0
1
CNT
DCDR
U/D
16
5
BYTE SELECTED
High
Low
A pulse is presented on this LSTTL-compatible output when the quadrature decoder
has detected a state transition.
This LSTTL-compatible output allows the user to determine whether the IC is
counting up or down and is intended to be used with the CNT
DCDR
and CNT
CAS
outputs. The proper signal U (high level) or D (low level) will be present before the
rising edge of the CNT
DCDR
and CNT
CAS
outputs.
A pulse is presented on this LSTTL-compatible output when the HCTL-2020 internal
counter overflows or underflows. The rising edge on this waveform may be used to
trigger an external counter.
These LSTTL-compatible tri-state outputs form an 8-bit output port through which
the contents of the 12/16-bit position latch may be read in 2 sequential bytes.
The high byte, containing bits 8-15, is read first (on the HCTL-2000, the most
significant 4 bits of this byte are set to 0 internally). The lower byte, bits 0-7,
is read second.
CNT
CAS
15
D0
D1
D2
D3
D4
D5
D6
D7
NC
1
15
14
13
12
11
10
9
1
19
18
17
14
13
12
11
6
Not connected – this pin should be left floating.
4
Switching Characteristics
Table 5. Switching Characteristics
Min/Max specifications at V
DD
= 5.0 ± 5%, T
A
= -40 to + 85° C.
Symbol Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
t
CLK
t
CHH
t
CD[1]
t
ODE
t
ODZ
t
SDV
t
CLH
t
SS[2]
t
OS[2]
t
SH[2]
t
OH[2]
t
RST
t
DCD
t
DSD
t
DOD
t
UDD
t
CHD
t
CLD
t
UDH
t
UDCS
t
UDCH
Clock period
Pulse width, clock high
Delay time, rising edge of clock to valid, updated count information on D0-7
Delay time, OE fall to valid data
Delay time, OE rise to Hi-Z state on D0-7
Delay time, SEL valid to stable, selected data byte
(delay to High Byte = delay to Low Byte)
Pulse width, clock low
Setup time, SEL before clock fall
Setup time, OE before clock fall
Hold time, SEL after clock fall
Hold time, OE after clock fall
Pulse width, RST low
Hold time, last position count stable on D0-7 after clock rise
Hold time, last data byte stable after next SEL state change
Hold time, data byte stable after OE rise
Delay time, U/D valid after clock rise
Delay time, CNT
DCDR
or CNT
CAS
high after clock rise
Delay time, CNT
DCDR
or CNT
CAS
low after clock fall
Hold time, U/D stable after clock rise
Setup time, U/D valid before CNT
DCDR
or CNT
CAS
rise
Hold time, U/D stable after CNT
DCDR
or CNT
CAS
rise
10
t
CLK
-45
t
CLK
-45
28
20
20
0
0
28
10
5
5
45
45
45
Min.
70
28
Max.
Units
ns
ns
65
65
40
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. t
CD
specification and waveform assume latch not inhibited.
2. t
SS
, t
OS
, t
SH
, t
OH
only pertain to proper operation of the inhibit logic. In other cases, such as 8 bit read operations, these setup and hold times do
not need to be observed.
Figure 3. Tri-State Output Timing.
5
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