32K x 36, 3.3V SYNCHRONOUS
BURST SRAM WITH 3.3V/2.5V
FLOW-THROUGH OUTPUTS
Integrated Device Technology, Inc.
PRELIMINARY
IDT71V537
FEATURES:
• 32K x 36 memory configuration
• Supports high performance system speed - up to 75 MHz
(8 ns Clock-to-Data Access)
•
LBO
input selects interleaved or linear burst mode
• Self-timed write cycle with global write control (
GW
), byte
write enable (
BWE
), and byte writes (
BW
x)
• Power down controlled by ZZ input
• The core operates with a 3.3V supply (+10/-5%) (V
DD
)
• I/O's can either operate at 3.3V (+10/-5%) or 2.5V (+0.4/
-0.2V) (V
DDQ
)
• I/O's are 5V - tolerant.
• Packaged in a JEDEC Standard 100-pin rectangular
plastic thin quad flatpack (TQFP)
DESCRIPTION:
The IDT71V537 is a 3.3V high-speed 1,179,648-bit SRAM
organized as 32K x 36 with full support of various processor
interfaces including the Pentium™ and PowerPC™. The flow-
through burst architecture provides cost-effective 2-1-1-1
performance for processors up to 75 MHz.
The IDT71V537 SRAM contains write, data-input, address
and control registers. There are no registers in the data output
path (flow-through architecture). Internal logic allows the
SRAM to generate a self-timed write based upon a decision
which can be left until the extreme end of the write cycle.
The burst mode feature offers the highest level of perfor-
mance to the system designer, as the IDT71V537 can provide
four cycles of data for a single address presented to the
SRAM. An internal burst address counter accepts the first
cycle address from the processor, initiating the access se-
quence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising
clock edge of the same cycle. If burst mode operation is
selected (
ADV
=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock
edges. The order of these three addresses will be defined by
the internal burst counter and the
LBO
input pin.
The IDT71V537 SRAM utilizes IDT's high-performance
3.3V CMOS process, and is packaged in a JEDEC Standard
14mm x 20mm 100-pin thin plastic quad flatpack (TQFP).
PIN DESCRIPTION SUMMARY
A
0
– A
14
Address Inputs
Chip Enable
Chips Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock Input
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Data Input/Output
Data Input/Output (Parity)
3.3V Array, 3.3V or 2.5V I/O
Array Ground, I/O Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
Power
Power
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
Synchronous
N/A
N/A
3604 tbl 01
CE
CS
0
,
CS
1
OE
GW
BWE
BW
1
-
BW
4
CLK
ADV
ADSC
ADSP
LBO
ZZ
I/O
0
-I/O
31
I/OP
1
-I/OP
4
V
DD
, V
DDQ
V
SS
, V
SSQ
The IDT logo is a registered trademark and CacheRAM is a trademark of Integrated Device Technology
Pentium is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc.
JULY 1996
9.
1
3604/-
IDT71V537
32K x 36, 3.3V SYNCHRONOUS BURST SRAM WITH 3.3V/2.5V FLOW-THROUGH OUTPUTS
COMMERCIAL TEMPERATURE RANGE
PIN DEFINITIONS
(1)
Symbol
A
0
-A
14
Pin Function
Address Inputs
Address Status
(Cache Controller)
Address Status
(Processor)
Burst Address
Advance
I/O
I
I
Active
N/A
LOW
Description
Synchronous Address inputs. The address register is triggered by a combination
of the rising edge of CLK and
ADSC
Low or
ADSP
Low and
CE
Low.
Synchronous Address Status from Cache Controller.
ADSC
is an active LOW
input that is used to load the address registers with new addresses.
ADSC
is
NOT GATED by
CE
.
ADSC
ADSP
ADV
I
LOW
Synchronous Address Status from Processor.
ADSP
is an active LOW input
that is used to load the address registers with new addresses.
ADSP
is gated
by
CE
.
Synchronous Address Advance.
ADV
is an active LOW input that is used to
advance the internal burst counter, controlling burst access after the initial
address is loaded. When this input is HIGH the burst counter is not incremented;
that is, there is no address advance.
I
LOW
BWE
Byte Write Enable
I
LOW
BW
1
-
BW
4
Synchronous byte write enable gates the byte write inputs
BW
1
-
BW
4
. If
BWE
is
LOW at the rising edge of CLK then
BW
X
inputs are passed to the next stage in
the circuit. A byte write can still be blocked if
ADSP
is LOW at the rising edge
of CLK. If
ADSP
is HIGH and
BW
X
is LOW at the rising edge of CLK then data
will be written to the SRAM. If
BWE
is HIGH then the byte write inputs are blocked
and only
GW
can initiate a write cycle.
Synchronous byte write enables. Each 9-bit byte has its own active LOW byte
write. Any active byte write causes all outputs to be disabled.
ADSP
LOW
disables all byte writes.
BW
1
-
BW
4
must meet specified setup and hold times with
respect to CLK.
Synchronous chip enable.
CE
is used with CS
0
and
CS
1
to enable the
IDT71V537.
CE
also gates
ADSP
.
This is the clock input. All timing references for the device are made with
respect to this input.
Synchronous active HIGH chip select. CS
0
is used with
CE
and
CS
1
to enable
the chip.
Synchronous active LOW chip select.
the chip.
Individual Byte
Write Enables
I
LOW
CE
CLK
CS
0
Chip Enable
Clock
Chip Select 0
Chip Select 1
Global Write
Enable
I
I
I
I
I
LOW
N/A
HIGH
LOW
LOW
CS
1
GW
CS
1
is used with
CE
and CS
0
to enable
Synchronous global write enable. This input will write all four 9-bit data bytes
when LOW on the rising edge of CLK.
GW
superceeds individual byte write
enables.
Synchronous data input/output (I/O) pins. Only the data input path is registered
and triggered by the rising edge of CLK. Outputs are Flow-through.
Asynchronous burst order selection DC input. When
LBO
is HIGH the Interleaved
(Intel) burst sequence is selected. When
LBO
is LOW the Linear (PowerPC)
burst sequence is selected.
LBO
is a static DC input and must not change state
while the device is operating.
LBO
has an internal pull-up resistor.
Asynchronous output enable. When
OE
is HIGH the I/O pins are in a high-
impedence state. When
OE
is LOW the data output drivers are enabled if
the chip is also selected.
3.3V core power supply inputs.
User selectable 3.3V or 2.5V I/O power supply inputs.
Core ground pins.
I/O ground pins.
NC pins are not electrically connected to the chip.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and
power down the IDT71V537 to its lowest power consumption level. Data
retention is guaranteed in Sleep Mode. ZZ has an internal pull-down resistor.
3604 tbl 02
I/O
0
-I/O
31
Data Input/Output
I/OP
1
-I/OP
4
I/O
I
N/A
LOW
LBO
Linear Burst
Order
OE
V
DD
V
DDQ
V
SS
V
SSQ
NC
ZZ
Output Enable
I
LOW
Power Supply
Power Supply
Ground
Ground
No Connect
Sleep Mode
N/A
N/A
N/A
N/A
N/A
I
N/A
N/A
N/A
N/A
N/A
HIGH
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
9.
2
IDT71V537
32K x 36, 3.3V SYNCHRONOUS BURST SRAM WITH 3.3V/2.5V FLOW-THROUGH OUTPUTS
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
CE#
Burst
Sequence
INTERNAL
ADDRESS
CLK
2
Binary
Counter
CLR#
ADSC
ADSP
A0–A14
CE#
ADDRESS
REGISTER
Byte 1
Write Register
Burst
Logic
15
A0*
A1*
Q0
Q1
32K x 36
BIT
MEMORY
ARRAY
2
A0,A1
15
A2–A14
36
36
GW
BWE
BW1
Byte 2
Write Register
Byte 1
Write Driver
9
Byte 2
Write Driver
BW2
Byte 3
Write Register
9
Byte 3
Write Driver
BW3
Byte 4
Write Register
9
Byte 4
Write Driver
BW4
CE
CS0
D
9
CS1
Q
Enable
Register
CE#
DATA INPUT
REGISTER
ZZ
Powerdown
OE
OUTPUT
BUFFER
OE
I/O0 – I/O31
I/OP1 - I/OP4
36
3604 drw 01
RECOMMENDED DC OPERATING
CONDITIONS WITH V
DDQ
AT 3.3V.
Symbol
V
DD
V
DDQ
V
SS
, V
SSQ
V
IH
V
IL
Parameter
Min.
Typ.
3.3
3.3
0
—
—
Max.
3.63
3.63
0
5.5
(2)
0.8
Unit
V
V
V
V
V
Core Supply Voltage 3.135
I/O Supply Voltage
Ground
Input High Voltage
Input Low Voltage
3.135
0
2.0
(1)
-0.5
(3)
RECOMMENDED DC OPERATING
CONDITIONS WITH V
DDQ
AT 2.5V.
Symbol
V
DD
V
DDQ
V
SS
, V
SSQ
V
IH
V
IL
Parameter
Min.
Typ.
3.3
2.5
0
—
—
Max.
3.63
2.9
0
5.5
(2)
0.7
Unit
V
V
V
V
V
Core Supply Voltage 3.135
I/O SupplyVoltage
Ground
Input High Voltage
Input Low Voltage
2.375
0
1.7
(1)
-0.3
(3)
3604 tbl 03
NOTE:
1. V
IH
and V
IL
as indicated is for both input and I/O pins.
2. V
IH
(max) = 6.0V for pulse width less than tCYC/2, once per cycle.
3. V
IL
(min) = -1.0V for pulse width less than tCYC/2, once per cycle.
NOTE:
3604 tbl 04
1. V
IH
and V
IL
as indicated is for both input and I/O pins.
2. V
IH
(max) = 6.0V for pulse width less than tCYC/2, once per cycle.
3. V
IL
(min) = -1.0V for pulse width less than tCYC/2, once per cycle.
9.
3
IDT71V537
32K x 36, 3.3V SYNCHRONOUS BURST SRAM WITH 3.3V/2.5V FLOW-THROUGH OUTPUTS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
CS
0
GW
BWE
OE
ADSC
ADSP
ADV
V
DD
V
SS
CLK
BW
4
BW
3
BW
2
BW
1
CS
1
CE
A
6
A
7
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP
3
I/O
16
I/O
17
V
DDQ
V
SSQ
I/O
18
I/O
19
I/O
20
I/O
21
V
SSQ
V
DDQ
I/O
22
I/O
23
V
SS
*
V
DD
NC
V
SS
I/O
24
I/O
25
V
DDQ
V
SSQ
I/O
26
I/O
27
I/O
28
I/O
29
V
SSQ
V
DDQ
I/O
30
I/O
31
I/OP
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
8
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
PK100-1
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/OP
2
I/O
15
I/O
14
V
DDQ
V
SSQ
I/O
13
I/O
12
I/O
11
I/O
10
V
SSQ
V
DDQ
I/O
9
I/O
8
V
SS
NC
V
DD
ZZ
I/O
7
I/O
6
V
DDQ
V
SSQ
I/O
5
I/O
4
I/O
3
I/O
2
V
SSQ
V
DDQ
I/O
1
I/O
0
I/OP
1
* Pin 14 does not have to be directly connected to
V
SS
as long as the input voltage is
≤
V
IL
3604 drw 02
LBO
ABSOLUTE MAXIMUM DC RATINGS
(1)
Symbol
V
TERM(2)
V
TERM(3)
T
A
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Com’l.
–0.5 to +5.5
–0.5 to +5.5
0 to +70
–55 to +125
–55 to +125
1.2
50
Unit
V
V
°C
°C
°C
W
mA
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
NC
NC
TOP VIEW
TQFP
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz, TQFP package)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
4
7
Unit
pF
pF
NOTE:
3604 tbl 06
1. This parameter is guaranteed by device characterization, but not prod-
uction tested.
NOTES:
3604 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
DD
, V
DDQ
and input terminals only.
3. I/O terminals.
9.
4
IDT71V537
32K x 36, 3.3V SYNCHRONOUS BURST SRAM WITH 3.3V/2.5V FLOW-THROUGH OUTPUTS
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING
TEMPERATURE AND SUPPLY VOLTAGE RANGE
(V
DD
= 3.3V +10/-5%)
Symbol
|I
LI
|
|I
LI
|
|I
LO
|
V
OL
(3.3V)
V
OH
(3.3V)
V
OL
(2.5V)
V
OH
(2.5V)
Parameter
Input Leakage Current
ZZ &
LBO
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Condition
V
DD
= Max., V
IN
= 0V to V
DD
V
DD
= Max., V
IN
= 0V to V
DD
Min.
—
—
—
—
2.4
—
1.7
Max.
5
30
5
0.4
—
0.7
—
Unit
µA
µA
µA
V
V
V
V
3604 tbl 07
CE
≥
V
IH
or
OE
≥
V
IH,
V
OUT
= 0V to V
DD
,
V
DD
= Max.
I
OL
= 5mA, V
DD
= Min.
I
OL
= –5mA, V
DD
= Min.
I
OL
= 5mA, V
DD
= Min.
I
OH
= –5mA, V
DD
= Min.
NOTE:
1. The ZZ pin has an internal pull-down resistor to V
SSQ
.
The
LBO
pin has an internal pull-up resistor to V
DDQ.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING
TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1)
(V
DD
= 3.3V +10/-5%, V
HD
= V
DDQ
–0.2V
,
V
LD
= 0.2V)
Symbol
I
DD
I
DDQ
I
SB
I
SBQ
I
SB1
I
SB1Q
I
ZZ
I
ZZQ
Parameter
Operating Core Power
Supply Current
Operating I/O Power
Supply Current
Standby Core Power
Supply Current
Standby I/O Power
Supply Current
Full Standby Core Power
Supply Current
Full Standby I/O Power
Supply Current
Full Sleep Mode Core
Power Supply Current
Full Sleep Mode I/O
Power Supply Current
Test Condition
Device Selected, Outputs Open, V
DD
= Max.,
V
IN
≥
V
IH
or
≤
V
IL
, f = f
MAX
(2)
Device Selected, Outputs Open, V
DDQ
= Max.,
V
IN
≥
V
IH
or
≤
V
IL
, f = f
MAX
(2)
Device Deselected, Outputs Open, V
DD
= Max.,
V
IN
≥
V
IH
or
≤
V
IL
, f = f
MAX
(2)
Device Deselected, Outputs Open,
V
DDQ
= Max., V
IN
≥
V
IH
or
≤
V
IL
, f = f
MAX
(2)
Device Deselected, Outputs Open, V
DD
= Max.,
V
IN
≥
V
HD
or
≤
V
LD
, f = 0
(2)
Device Deselected, Outputs Open,
V
DDQ
= Max., V
IN
≥
V
HD
or
≤
V
LD
, f = 0
(2)
ZZ
≥
V
HD
, V
DD
= Max.
ZZ
≥
V
HD
, V
DDQ
= Max.
75MHz
210
15
70
3
25
3
5
1
66MHz
205
15
65
3
25
3
5
1
60MHz
200
15
60
3
25
3
5
1
50MHz
185
15
55
3
25
3
5
1
Unit
mA
mA
mA
mA
mA
mA
mA
mA
3604 tbl 07
NOTES:
1. All values are maximum guaranteed values.
2. At f = f
MAX,
address inputs are cycling at the maximum frequency of read cycles of 1/t
CYC
while
ADSC
= LOW; f=0 means no address input lines are changing.
6
5
4
DATA OUT
+3.3V
317Ω
∆
tCD 3
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
3604 drw 03
351Ω
5pF
3604 drw 04
Figure 2. High-Impedence Test Load
(for t
OHZ
, t
CHZ
, t
OLZ
, and t
DC1)
* Including scope and jig
Figure 1. Lumped Capacitive Load, Typical Derating
9.
5
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