June 1996
NDT452AP
P-Channel Enhancement Mode Field Effect Transistor
General Description
Power SOT P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance
and provide superior switching performance. These devices
are particularly suited for low voltage applications such as
notebook computer power management and DC motor
control.
Features
-5A, -30V. R
DS(ON)
= 0.065
Ω
@ V
GS
= -10V
R
DS(ON)
= 0.1
Ω
@ V
GS
= -4.5V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
________________________________________________________________________________
D
D
G
D
S
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
P
D
Maximum Power Dissipation
T
A
= 25°C unless otherwise noted
NDT452AP
-30
±20
(Note 1a)
Units
V
V
A
-5
- 15
(Note 1a)
(Note 1b)
(Note 1c)
3
1.3
1.1
-65 to 150
W
T
J
,T
STG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
42
12
°C/W
°C/W
* Order option J23Z for cropped center drain lead.
© 1997 Fairchild Semiconductor Corporation
NDT452AP Rev. B1
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(ON)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= -250 µA
V
DS
= -24 V, V
GS
= 0 V
T
J
= 55°C
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= -250 µA
T
J
= 125°C
Static Drain-Source On-Resistance
V
GS
= -10 V, I
D
= -5.0 A
T
J
= 125°C
V
GS
= -4.5 V, I
D
= -4.3 A
I
D(on)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
On-State Drain Current
V
GS
= -10 V, V
DS
= -5 V
V
GS
= -4.5 V, V
DS
= -5 V
Forward Transconductance
V
DS
= -10 V, I
D
= -5.0 A
V
DS
= -15 V, V
GS
= 0 V,
f = 1.0 MHz
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
690
430
160
pF
pF
pF
-15
-5
7
S
-1
-0.7
-1.6
-1.2
0.052
0.075
0.085
-30
-1
-10
100
-100
V
µA
µA
nA
nA
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
-2.8
-2.2
0.065
0.13
0.1
A
V
Ω
SWITCHING CHARACTERISTICS
(Note 2)
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= -10 V,
I
D
= -5.0 A, V
GS
= -10 V
V
DD
= -10 V, I
D
= -1 A,
V
GEN
= -10 V, R
GEN
= 6
Ω
9
20
40
19
22
3.2
5.2
20
30
50
40
30
ns
ns
ns
ns
nC
nC
nC
NDT452AP Rev. B1
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
Reverse Recovery Time
V
GS
= 0 V, I
S
= -2.5 A
(Note 2)
-2.5
-0.85
-1.2
100
A
V
ns
V
GS
= 0 V, I
F
= -2.5 A, dI
F
/dt = 100 A/µs
P
D
(
t
) =
T
J
−
T
A
R
θ
JA
(
t
)
=
T
J
−
T
A
R
θ
JC
+
R
θ
C
(
t
)
A
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 42
o
C/W when mounted on a 1 in
2
pad of 2oz copper.
b. 95
o
C/W when mounted on a 0.066 in
2
pad of 2oz copper.
c. 110
o
C/W when mounted on a 0.0123 in
2
pad of 2oz copper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDT452AP Rev. B1
Typical Electrical Characteristics
-20
3
V
GS
= -10V
I
D
, DRAIN-SOURCE CURRENT (A)
-5.0
-4.5
R
DS(on)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
-6.0
-15
V
GS
= -3.5V
2.5
- 4.0
-4.5
-5.0
-4.0
-10
2
-3.5
-5
1.5
-6.0
-10
-3.0
1
0
0
-1
-2
-3
V
DS
, DRAIN-SOURCE VOLTAGE (V)
-4
0.5
0
-4
-8
-12
I
D
, DRAIN CURRENT (A)
-16
-20
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with Gate
Voltage and Drain Current.
1.6
2
I
D
= -5.0A
DRAIN-SOURCE ON-RESISTANCE
1.4
DRAIN-SOURCE ON-RESISTANCE
V
GS
= -10V
R
DS(on)
, NORMALIZED
V
GS
= -10V
R
DS(ON)
, NORMALIZED
1.5
1.2
TJ = 125°C
1
25°C
1
0.8
-55°C
0.6
-50
0.5
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
J
125
150
0
-4
I
D
-8
-12
, DRAIN CURRENT (A)
-16
-20
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
-20
GATE-SOURCE THRESHOLD VOLTAGE
1.2
V
DS
= -10V
I
D
, DRAIN CURRENT (A)
-15
T J = -55°C
125°C
25°C
V
th
, NORMALIZED
1.1
V
DS
= V
GS
I
D
= -250µA
1
-10
0.9
0.8
-5
0.7
0
-1
-2
-3
-4
-5
V
GS
, GATE TO SOURCE VOLTAGE (V)
-6
0.6
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation with
Temperature.
NDT452AP Rev. B1
Typical Electrical Characteristics
1.1
DRAIN-SOURCE BREAKDOWN VOLTAGE
1.08
1.06
1.04
1.02
1
0.98
0.96
0.94
-50
20
I
D
= -250µA
-I
S
, REVERSE DRAIN CURRENT (A)
10
5
V
GS
= 0V
BV
DSS
, NORMALIZED
1
TJ = 125°C
25°C
-55°C
0.1
0.01
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0.001
0
0.4
0.8
1.2
1.6
-V
SD
, BODY DIODE FORWARD VOLTAGE (V)
2
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature
.
2000
10
I
D
= -5.0A
, GATE-SOURCE VOLTAGE (V)
1000
CAPACITANCE (pF)
8
V
DS
= -5V
-10V
-20V
C iss
500
6
C oss
300
200
4
f = 1 MHz
V
GS
= 0 V
C rss
100
0.1
-V
0.2
0.5
1
2
5
10
30
0
0
5
10
15
Q
g
, GATE CHARGE (nC)
20
25
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
GS
2
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics.
-V
DD
t
d(on)
t
on
t
off
t
r
90%
t
d(off)
90%
V
IN
D
R
L
V
OUT
V
OUT
10%
t
f
V
GS
R
GEN
10%
90%
G
DUT
S
V
IN
10%
50%
50%
PULSE WIDTH
INVERTED
Figure 11. Switching Test Circuit.
Figure 12. Switching Waveforms.
NDT452AP Rev. B1
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
