®
Integrated Device Technology, Inc.
SELF-TIMED BiCMOS ECL
STATIC RAM
64K (16K x 4-BIT) STRAM
IDT10496RL
IDT100496RL
IDT101496RL
FEATURES:
• 16,384-words x 4-bit organization
• Self-Timed, with registers on inputs and latches on
outputs
• Balanced Read/Write cycle time: 10/12/15 ns
• Access time: 10/12/15 ns (max.)
• Fully compatible with ECL logic levels
• Through-hole DIP and surface-mount packages
DESCRIPTION:
The IDT10496RL, IDT100496RL and IDT101496RL are
65,536-bit high-speed BiCEMOS™ ECL static random ac-
cess memories organized as 16K x 4, with inputs and outputs
fully compatible with ECL levels. Clocked registers on inputs
and latches on outputs, and the self-timed write operation,
provide enhanced system performance over conventional
RAMs, providing easier design and improved system level
cycle times.
Inputs are captured by the leading edge of an externally
supplied differential clock. The small input valid window re-
quired means more margin for system skews. Logic-to-memory
propagation delay is included in device cycle time calculation,
allowing this device to deliver better system performance than
asynchronous SRAMs and glue logic.
Write timing is controlled internally based on the clock.
Write Enable has no special requirements. The device allows
balanced read and write cycle times, and reads and writes can
be inserted in any order.
FUNCTIONAL BLOCK DIAGRAM
A
0
R
E
G
I
S
T
E
R
DECODER
65,536-BIT
MEMORY ARRAY
REF. VOLTAGE
GENERATOR
V
CC
V
EE
V
BB
A
13
R
E
G
I
S
T
E
R
D
0
D
1
D
2
D
3
SENSE AMPS
AND READ/WRITE
CONTROL
WRITE-PULSE
GENERATOR
A
L
A
T
C
H
MUX
Q
0
Q
1
Q
2
Q
3
*
B
WE
CS
R
E
G
A/B
L
A
T
C
H
CLK
CLK
*
*
HOLD/OPEN
2771 drw 01
BiCEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©
1992 Integrated Device Technology, Inc.
AUGUST 1992
1
IDT10496RL, IDT100496RL, IDT101496RL
HIGH SPEED BiCMOS ECL SELF-TIMED STATIC RAM 64K (16K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
CS
D
0
D
1
D
2
D
3
Q
0
Q
1
Vcc
Vcc
Q
2
Q
3
A
0
A
1
A
2
A
3
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
WE
V
BB
CLK
CLK
NC
NC
A
13
A
12
V
EE
A
11
A
10
A
9
A
8
A
7
A
6
A
5
400-Mil-Wde
CERAMIC PACKAGE
C32-2
2771 drw 03
300-Mil-Wide
PLASTIC SOJ PACKAGE
SO32-2
2771 drw 04
2771 drw 02
TOP VIEW
PIN DESCRIPTION
Symbol
A
0
through A
13
D
0
through D
3
Q
0
through Q
3
Data Inputs
Data Outputs
Write Enable Input
Chip Select Input (Internal pull down)
Pin Name
Address Inputs
WE
CS
Hi-Rel Die
For Hybrid and MCM
Applications
2771 drw 05
CLK,
V
BB
V
EE
V
CC
NC
CLK
Differential Clock Inputs
Reference Voltage Output (≈1.32V)
More Negative Supply Voltage
Less Negative Supply Voltage
No Connect - not internally bonded
LOGIC SYMBOL
D
0
D
1
D
2
D
3
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
CAPACITANCE
(T
A
=+25°C, f=1.0MHz)
DIP
Symbol
C
INCLK
Parameter
Input
Capacitance
CLK/
CLK
Input
Capacitance
except CLK/
CLK
Output
Capacitance
Typ.
Max.
SOJ
Typ.
Max.
Unit
pF
6
–
3
–
C
IN
4
–
3
–
pF
C
OUT
6
–
3
–
pF
Q
0
Q
1
Q
2
Q
3
TRUTH TABLE
(1)
CS
H
L
L
WE
X
H
L
CLK
Data
OUT (2)
L
RAM Data
WRITE Data
Function
Deselected
Read
Write
CLK CLK WE CS
NOTES:
1. H=High, L=Low, X=Don’t Care
2. DATA
OUT
initiated by falling edge of CLK.
16Kx4
STRAM
2771 drw 05
2
IDT10496RL, IDT100496RL, IDT101496RL
HIGH SPEED BiCMOS ECL SELF-TIMED STATIC RAM 64K (16K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
A
Rating
Terminal Voltage
With Respect to GND
Operating
Temperature
10K
100K
101K
Ceramic
Plastic
Value
+0.5 to -7.0
0 to +75
0 to +85
0 to +75
-55 to +125
-65 to +150
-55 to +125
1.5
-50
Unit
V
°C
AC/DC ELECTRICAL OPERATING RANGES
I/O
10K
100K
V
EE
-5.2V
±
5%
-4.5V
±
5%
T
A
0 to +75°C, air flow exceeding 2 m/sec
0 to +85°C, air flow exceeding 2 m/sec
2760 tbl 05
101K -4.75V to -5.46V 0 to +75°C, air flow exceeding 2 m/sec
T
BIAS
T
STG
P
T
I
OUT
Temperature Under Bias
Storage
Temperatuure
°C
°C
W
mA
Power Dissipation
DC Output Current
(Output High)
NOTE:
2760 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(1)
10K
Symbol
V
OH
Parameter
Output HIGH Voltage
(V
IN
= V
IH(Max)
or V
IL(Min)
)
Output LOW Voltage
(V
IN
= V
IH(Max)
or V
IL(Min)
)
Output Threshold HIGH Voltage
(V
IN
= V
IH(Min)
or V
IL(Max)
)
Output Threshold LOW Voltage
(V
IN
= V
IH(Min)
or V
IL(Max)
)
Input HIGH Voltage
(Guaranteed Input Voltage
High for All Inputs)
Input LOW Voltage
(Guaranteed Input Voltage
Low for All Inputs)
Input HIGH Current
CS
V
IN
= V
IH(Max)
Others
Input LOW Current
V
IN
= V
IL(Min)
CS
Others
Supply Current
Min.
-1000
-960
-900
-1870
-1850
-1830
-1020
-980
-920
—
—
—
-1145
-1105
-1045
-1870
-1850
-1830
—
—
0.5
-50
-260
Max.
-840
-810
-720
-1665
-1650
-1625
—
—
—
-1645
-1630
-1605
-840
-810
-720
-1490
-1475
-1450
220
110
170
90
—
TA
0°C
25°C
75°C
0°C
25°C
75°C
0°C
25°C
75°C
0°C
25°C
75°C
0°C
25°C
75°C
0°C
25°C
75°C
—
—
—
—
—
100K/101K
Min.
-1025
Max.
-880
Unit
mV
V
OL
-1810
-1620
mV
V
OHC
-1035
—
mV
V
OLC
—
-1610
mV
V
IH
-1165
-880
mV
V
IL
-1810
-1475
mV
I
IH
—
—
0.5
-50
-240 (100K)
-260 (101K)
220
110
170
90
—
—
µA
µA
µA
µA
mA
I
IL
I
EE
NOTE:
1. RL = 50Ω to -2V, air flow exceeding 2 m/sec.
2760 tbl 05
3
IDT10496RL, IDT100496RL, IDT101496RL
HIGH SPEED BiCMOS ECL SELF-TIMED STATIC RAM 64K (16K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
AC TEST LOAD CONDITION
V
CC
(GND)
AC TEST INPUT PULSE
-0.9V
DATA
OUT
80%
20%
-1.7V
50
Ω
30pF*
t
R
t
R
= t
F
= 1.5ns typ.
t
F
0.01
µ
F
V
EE
-2.0V
* Includes probe and jig
capacitance.
2771 drw 07
Note: All timing measurements are
referenced to 50% input levels.
2771 drw 08
RISE/FALL TIME
Symbol
tR
tF
Parameter
Output Rise Time
Output Fall Time
Min.
—
—
Typ.
1.5
1.5
Max.
—
—
Unit
ns
ns
2771 tbl 06
FUNCTIONAL DESCRIPTION
The IDT10496RL, IDT100496RL and IDT101496RL Self-
Timed BiCMOS ECL static RAMs (STRAM) provide high
speed with low power dissipation typical of BiCMOS ECL.
On-chip logic additionally helps improve system performance.
The ECL-101K meets electrical specifications that combine
the ECL-100K temperature and voltage compensated output
levels with the high-speed of ECL-10K V
EE
compatibility (-
5.2V).
As can be seen in the Functional Block Diagram on the title
page, this device contains clocked input registers to sample
and hold addresses, input data, and control status. Inputs are
sampled on the rising edge of the clock (CLK) input (falling
edge of CLK). In the case of a write cycle, the memory cell is
written during the clock-high time, and write data conducted to
the outputs. Output data flows out the output latch and is held
into the next cycle.
READ TIMING
In a typical read cycle, the read address is captured by the
rising edge of clock, as at
below. Then, when clock goes
low, the read data for the read address clocked in at
is gated
through the output latch to the output pins. There is a short
delay from falling clock to output ready, called t
DR
(see Read
Cycle Timing). If the clock-high time (t
WH
) is shorter than the
inherent access-time of the cell, output is guaranteed valid
after the specified t
ACC
. But if t
WH
is longer than the cell ac-
cess-time, output data will be valid t
DR
after clock goes low.
Thus, the time it takes from clock-to-output for any given
FUNCTIONAL DESCRIPTION TIMING EXAMPLE
t
CYC
CLK
READ
CS
DESELECT
WRITE
READ
WRITE
WRITE
READ
READ
ADDR
DATA
IN
WE
DATA
OUT
t
ACC
READ DATA
DESELECT
WRITE DATA
READ DATA
WRITE DATA
WRITE DATA
READ DATA
2771 drw 08
4
IDT10496RL, IDT100496RL, IDT101496RL
HIGH SPEED BiCMOS ECL SELF-TIMED STATIC RAM 64K (16K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
address (the latency, or t
ACC
) is
t
ACC
= t
ACC
or (t
WH
+ t
DR
),
whichever is larger.
The output latch takes some time to change state for the
next cycle, but this time is very short. Therefore, data hold time
from clock low (t
DH
) is specified as zero minimum hold time.
DESELECT TIMING
Because the outputs are latched, they will continue to drive
the output pins until a disable state is clocked through the
device. The deselected state is achieved by de-asserting chip
select (CS high) at rising edge of clock. This case occurs at
below. Outputs then attain the disable state (low) t
ACC
later.
Status of other inputs do not effect the disabling of the device
when chip select is de-asserted with the proper relation to
clock.
WRITE TIMING
Write cycles are identical to read cycles, except that write
enable and write data need also be supplied, with the appro-
priate setup and hold timing. The device has on-chip timing
that handles all aspects of writing data into the addressed
RAM cell without the need for external write-pulse generation.
The timing logic uses the clock-high time as the write pulse,
and thus determines the minimum clock-high time, t
WH
.
In addition to writing to the RAM cell, the write data is fed
to the output register by a multiplexer, so that write data is
available on the output pins in the appropriate time slot (i.e.
after t
WH
+ t
DR
). This function is sometimes called “Transpar-
ent Write,” and is useful for write-through cache applications.
Thus the input data sampled at
is available on the output at
the end of the cycle.
There are no restrictions on the order of read cycles and
write cycles.
5
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