Data Sheet, Rev 1.00, Jun. 2005
HYS64T32000HDL–[2.5/…/5]–B
HYS64T64020HDL–[2.5/…/5]–B
HYS64T128021HDL–[2.5/…/5]–B
200-Pin SO-DIMM DDR2 SDRAM Modules
DDR2 SDRAM
SO-DIMM SDRAM
RoHS Compliant
Memory Products
N e v e r
s t o p
t h i n k i n g .
Edition 2005-06
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
©
Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
HYS64T32000HDL–[2.5/…/5]–B HYS64T64020HDL–[2.5/…/5]–B HYS64T128021HDL–[2.5/…/5]–B
Revision History: 2005-06, Rev 1.00
Previous Version:
Page
Subjects (major changes since last revision)
Final data sheet
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send us your proposal (including a reference to this document) to:
techdoc.mp@infineon.com
Template: mp_a4_s_rev314 / 3 / 2005-05-02
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
Table of Contents
1
1.1
1.2
2
2.1
2.2
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
4
5
6
Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configurations and Block Diagrams
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
DD
Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
DD
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
19
19
21
26
27
35
37
SPD Codes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Package Outlines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Data Sheet
4
Rev 1.00, 2005-06
05122005-2TKP-OM7N
200-Pin SO-DIMM DDR2 SDRAM Modules
DDR2 SDRAM
HYS64T32000HDL–[2.5/…/5]–B
HYS64T64020HDL–[2.5/…/5]–B
HYS64T128021HDL–[2.5/…/5]–B
1
Overview
This chapter gives an overview of the 200-Pin SO-DIMM DDR2 SDRAM Modules product family and describes its
main characteristics.
1.1
•
Features
•
•
•
•
•
•
•
•
•
•
Programmable self refresh rate via EMRS2 setting
Programmable partial array refresh via EMRS2
settings
DCC enabling via EMRS2 setting
All inputs and outputs SSTL_1.8 compatible
Off-Chip Driver Impedance Adjustment (OCD) and
On-Die Termination (ODT)
Serial Presence Detect with E
2
PROM
UDIMM and EDIMM Dimensions (nominal):
30 mm high, 133.35 mm wide
Based on standard reference layouts Raw Card “A”,
“C”,”E”
RoHS compliant products
1)
All speed grades faster than DDR400 comply with
DDR400 timing specifications.
•
•
•
•
•
200-Pin PC2–6400, PC2–5300, PC2–4200 and
PC2–3200 DDR2 SDRAM memory modules for use
as main memory when installed in systems such as
mobile personal computers.
32M
×
64, 64M
×
64 and 128M
×
64 module
organization,and 32M
×
16, 64M
×
8 chip
organization
Standard Double-Data-Rate-Two Synchronous
DRAMs (DDR2 SDRAM) with a single + 1.8 V
(± 0.1 V) power supply
Built with 512-Mbit DDR2 SDRAMs in P-TFBGA-84
and P-TFBGA-60 chipsize packages
Programmable CAS Latencies (3, 4 and 5), Burst
Length (8 & 4) and Burst Type
Auto Refresh (CBR) and Self Refresh
Performance
–2.5
Table 1
Product Type Speed Code
Speed Grade
max. Clock Frequency
@CL6
@CL5
@CL4
@CL3
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
–3
333
333
333
200
12
12
45
57
–3S
333
333
266
200
15
15
45
60
Unit
PC2–6400 6–6–6 PC2–5300 4–4–4 PC2–5300 5–5–5 —
f
CK6
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
400
333
266
200
15
15
45
60
MHz
MHz
MHz
ns
ns
ns
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January
2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and
polybrominated biphenyl ethers.
Data Sheet
5
Rev 1.00, 2005-06
05122005-2TKP-OM7N
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
