MK3727E
L
OW
C
OST
27 MH
Z
3.3 V
OLT
VCXO
Description
The MK3727E combines the functions of a VCXO
(Voltage Controlled Crystal Oscillator) and PLL (Phase
Locked Loop) frequency doubler onto a single chip.
Used in conjunction with an external pullable quartz
crystal, this monolithic integrated circuit replaces more
costly hybrid (canned) VCXO devices. The MK3727E is
designed primarily for data and clock recovery
applications within end products such as set-top box
receivers.
The MK3727E exhibits a moderate VCXO gain of 120
ppm/V typical, when used with a high quality external
pullable quartz crystal.
The frequency of the on-chip VCXO is adjusted by an
external control voltage input into pin VIN. Because
VIN is a high impedance input, it can be driven directly
from an PWM RC integrator circuit. Frequency output
increases with VIN voltage input. The usable range of
VIN is 0 to 3 V.
Features
•
MK3727E offers 24-36 MHz output frequency range
(output frequency = 2x crystal frequency) and
improved power supply noise rejection
•
Uses an inexpensive 12 to 18 MHz external crystal
•
Ideal for set-top box applications using 13.5 MHz
external pullable crystal to generate lock 27 MHz
clock transport video clock
•
Ideal for ADSL applications using 17.664 MHz
external pullable crystal to generate locked 35.328
MHz clock physical layer clock
•
On-chip VCXO with guaranteed pull range of ±115
ppm minimum
•
•
•
•
VCXO input tuning voltage 0 to 3.3 V
Packaged in 8 pin SOIC (150 mil wide)
Available in Pb (lead) free packaging
Exact drop-in replacement for MK3727S
Block Diagram
VIN
12-18 MHz
Pullable
Crystal
X1
X2
Voltage
Controlled
Crystal
Oscillator
PLL
Frequency
Doubler
24-36 MHz
(2x Crystal Frequency)
MDS 3727E D
Integrated Circuit Systems
l
1
5 25 Race Street, San Jose, CA 9 512 6
l
Revision 042105
tel (40 8) 2 97-12 01
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w w w. i c s t . c o m
MK3727E
L
OW
C
OST
27 MH
Z
3.3 V
OLT
VCXO
External Component Selection
The MK3727E requires a minimum number of external
components for proper operation.
Shunt Capacitance, C0
C0/C1 Ratio
Equivalent Series Resistance
7 pF Max
250 Max
35
Ω
Max
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD (pin 2) and GND (pin 4), as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
The third overtone mode of the crystal and all spurs
must be >100 ppm distant from 3x the fundamental
resonance measured with a physical load of 14 pF.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the MK3727E. There should be no vias
between the crystal pins and the X1 and X2 device
pins. There should be no signal traces underneath or
close to the crystal.
Crystals can be made to resonate either at the
fundamental frequency, or on the third, fifth, or even
higher overtone. VCXO crystals are always
fundamental mode, because overtone modes are much
less pullable and require additional oscillator circuitry
for proper operation.
The third overtone mode is not necessarily at exactly
three times the fundamental frequency. The
mechanical properties of the quartz element dictate the
position of the overtones relative to the fundamental,
and in a VCXO circuit, the third overtone is not typically
exactly three times the fundamental, or the oscillator
circuit may excite both the fundamental and overtone
modes simultaneously. This will cause a nonlinearity in
the transfer curve such as the one in Figure 3. This
potential problem is why VCXO crystals are required to
be tested for absence of any activity inside a +/-100
ppm window at three times the fundamental frequency.
Series Termination Resistor
When the PCB trace between the clock output (CLK,
pin 5) and the load is over 1 inch, series termination
should be used. To series terminate a 50
Ω
trace (a
commonly used trace impedance) place a 33
Ω
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
Ω
.
Quartz Crystal
The MK3727E VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To
assure the best system performance (frequency pull
range) and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the
following section shown must be followed.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The MK3727E incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the MK3727E is designed to have zero frequency
error when the total of on-chip + stray capacitance is
14pF.
Recommended Crystal Parameters:
Initial Accuracy at 25
°
C
Temperature Stability
Aging
Load Capacitance
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
The procedure for determining the value of these
capacitors can be found in application note MAN05.
±20 ppm
±30 ppm
±20 ppm
14 pf
MDS 3727E D
Integrated Circuit Systems
l
3
525 Ra ce Stree t, Sa n Jose, CA 951 26
l
Revision 042105
te l (4 08) 297 -1 201
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w w w. i c st . c o m
MK3727E
L
OW
C
OST
27 MH
Z
3.3 V
OLT
VCXO
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3727E. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70
°
C
-65 to +150
°
C
260
°
C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Reference crystal parameters
Min.
0
+3.15
Typ.
Max.
+70
+3.45
Units
°
C
V
Refer to page 3
MDS 3727E D
Integrated Circuit Systems
l
4
525 Ra ce Stree t, Sa n Jose, CA 951 26
l
Revision 042105
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MK3727E
L
OW
C
OST
27 MH
Z
3.3 V
OLT
VCXO
DC Electrical Characteristics
VDD=3.3 V ±5%
, Ambient temperature 0 to +70
°
C, unless stated otherwise
Parameter
Operating Voltage
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
Operating Supply Current
Short Circuit Current
VIN, VCXO Control Voltage
Symbol
VDD
V
OH
V
OL
V
OH
IDD
I
OS
V
IA
Conditions
I
OH
= -12 mA
I
OL
= 12 mA
I
OH
= -4 mA
Output = 27 MHz,
no load
Min.
3.15
2.4
Typ.
Max.
3.45
0.4
Units
V
V
V
V
VDD-0.4
10
±50
0
3.3
mA
mA
V
AC Electrical Characteristics
VDD = 3.3 V ±5%,
Ambient Temperature 0 to +70
°
C, unless stated otherwise
Parameter
Output Frequency
Crystal Pullability
VCXO Gain
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Maximum Output Jitter,
short term
Symbol
F
O
F
P
t
OR
t
OF
t
D
t
J
Conditions
VCXO Crystal frequency =
1/2 Output
0V< VIN < 3.3 V, Note 1
VIN = VDD/2 + 1 V, Note 1
0.8 to 2.0 V, C
L
=15 pF
2.0 to 0.8 V, C
L
=15 pF
Measured at 1.4 V, C
L
=15 pF
C
L
=15 pF
Min.
24
+ 115
Typ.
Max. Units
36
MHz
ppm
120
1.5
1.5
40
50
100
60
ppm/V
ns
ns
%
ps
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
MDS 3727E D
Integrated Circuit Systems
l
5
525 Ra ce Stree t, Sa n Jose, CA 951 26
l
Revision 042105
te l (4 08) 297 -1 201
l
w w w. i c st . c o m
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