9Mb Pipelined
QDR™ SRAM
Burst of 4
x
x
Advance
Information
IDT71T64805
Features
9Mb Density (512K x 18)
Separate Independent Read and Write Data Ports
— Supports concurrent transactions
333 MHz Data Rate for High Bandwidth Applications
Fast Clock-to Valid access times
— 2.5ns for 166 MHz version
4-Word Burst for reduced address bus frequency
(same as the external clock rate)
Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 333 MHz)
Two input clocks (K and
K),
using rising edges only, for
precise DDR timing
Two output clocks (C and
C)
compensate for clock skew
and flight time mismatches
— Clock and data delivered together to receiving device
Single multiplexed address input bus latches address
inputs for both READ and WRITE ports
Separate Port Enables for depth expansion
Synchronous internally self-timed writes
2.5V core power supply with HSTL Inputs and Outputs
165-ball, 1.0mm pitch 13mm x 15mm fBGA package
Variable drive HSTL output buffers
JTAG Interface
Description
The IDT71T64805 is a 2.5V synchronous pipelined SRAM equipped
with QDR™ architecture. QDR architecture consists of two separate
ports to access the memory array. The Read port has dedicated Data
Outputs to support Read operations, and the Write Port has dedi-
cated Data Inputs to support Write operations. QDR architecture has
separate data inputs and data outputs to completely eliminate the
need to “turn-around” the data bus required with common I/O de-
vices. Access to each port is accomplished through a common ad-
dress bus. Addresses for Read and Write addresses are latched on
alternate rising edges of the input (K) clock. Accesses to the IDT71T64805
Read and Write ports are completely independent of one another. In
order to maximize data throughout, both Read and Write ports are equipped
with Double Data Rate (DDR) interfaces. Each address location is asso-
ciated with four 18-bit words that burst sequentially into or out of the
device. Since data can be transferred into and out of the device on every
rising edge of both input clocks (K/K and C/C), memory bandwidth is
maximized while simplifying system design by eliminating bus “turn-
arounds.”
Depth expansion is accomplished with Port Enables for each port.
Port enables allow each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or
K
input clocks. All data outputs pass through output registers
controlled by the C or
C
input clocks. Writes are conducted with on-
chip synchronous self-timed write circuitry.
x
x
x
x
x
x
x
x
x
x
x
x
x
Pin Description Summary
A
0
- A
16
Address Inputs
Read Port Enable
Write Port Enable
Individual Byte Write Selects
Clock signals for Data, Address and Control Inputs
Data Output Clocks
Data Input
Data Output
Output Impedance Matching Input
JTAG Inputs
JTAG Output
Reference Voltage Input
Core and Output Power
Ground
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Supply
Supply
Synchronous
Synchronous
Synchronous
Synchronous
N/A
N/A
Synchronous
Synchronous
Static
N/A
N/A
Static
Static
Static
5284 tbl 01
RPE
WPE
BW
0
,
BW
1
K,
K
C,
C
D
0
-
D
17
Q
0
-
Q
17
ZQ
TMS, TDI, TCK
TDO
V
REF
V
DD,
V
DDQ
V
SS
QDR SRAMs and Quad Data Rate comprise a new family of products developed by IDT Inc., Cypress Semiconductor and Micron Technology.
AUGUST 2000
DSC-5284/04
1
©2000 Integrated Device Technology, Inc.
IDT71T64805, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 4
Advance Information
Commercial Temperature Range
Pin Definitions
Symbol
Pin Function
I/O
Active
Description
Address inputs. Sampled on the rising edge of the K clock during active read and write
operations. These address inputs are multiplexed for both Read and Write operations. The
address for each port can be latched on alternating rising edges of the K clock. Internally, the
device is organized 128Kx72 and delivered externally in four 18-bit words. Therefore, only 17
address inputs are needed to access the entire memory array. These inputs are ignored
when appropriate port is deselected. If both Read and Write ports are selected, these inputs
will be used to initiate a Read request if there are no pending transactions.
Read Port Enable. Sampled on the rising edge of positive input clock (K). When active, a Read
operation is initiated. Deasserting will cause the Read port to be deselected. When deselected,
the pending access is allowed to complete and the output drivers are automatically tri-stated
following the next rising edge of the C clock. The IDT71T64805 is organized internally as
128Kx72. Each read access consists of a burst of four sequential 18-bit transfers over two clock
cycles. The entire burst of four data words should be allowed to complete. Initiating Read
accesses on two consecutive K clock rises is not a valid operation and the second Read
request will be ignored.
Write Port Enable. Sampled on the rising edge of the K clock. When asserted active, a write
operation is initiated. Deasserting will deselect the Write port. When deselected, the pending
access is allowed to complete. The IDT71T64805 is organized internally as 128Kx72. Each
write access consists of a burst of four sequential 18-bit transfers over two clock cycles. The
entire burst of four data words should be allowed to complete. Initiating Write accesses on
two consecutive K clock rises is not a valid operation and the second Write request will be
ignored.
Byte Write Enables 0 and 1. Sampled on the rising edge of the K and
K
clocks during write
operations. Used to select which byte is written into the device during the current portion of
the write operations. Bytes not written remain unaltered.
BW
0
controls D
[8:0]
while
BW
1
controls D[
17:9]
.
BW
0
and
BW
1
are sampled on same edg e as D[17:0]. Deselecting a Byte
Write Enable will cause the corresponding byte of data to be ignored and not written into the
device.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs (data,
address and control) to the device and drive out data through Q[17:0] when in single clock
mode. All accesses are initiated on the rising edge of K.
Negative Input Clock Input.
K
is used to capture synchronous inputs (data and control) being
presented to the device and drive out data through Q[17:0] when in single clock mode.
Positive Output Clock Input. C is used in conjuction with
C
to clock out the Read data from the
device. C and
C
can travel with the data to the receiving device. When used in this way C and
C
can be used to de-skew the flight times of various devices on the board (see application
example).
Negative Output Clock Input.
C
is used in conjunction with C to clock out the Read data from
the device. C and
C
can travel with the data to the receiving device. When used in this way C
and
C
can be used to de-skew the flight times of various device s on the board (see
application example).
Data Input signals, sampled on the rising edge of K and
K
clocks during the data portion of a
valid write operation.
Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and
C
clocks during Read operations (or
K and
K
when in single clock mode). When the read is deselected, Q[17:0} are
automatically tri-stated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. Q
[17:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternately, this pin can be connected to directly to V
DD
,
which enables the minimum impedance mode. This pin cannot be connected directly to V
ss
or left unconnected.
5284 tbl 02a
A
0
- A
16
Address Inputs
Input
N/A
RPE
Read port
Enable
Input
Low
WPE
Write Port
Enable
Input
Low
BW
0
,
BW
1
Individual Byte
Write Enables
Input
Low
K
Master Clock
Input
N/A
K
Master Clock
Input
N/A
C
Output Data
Clock
Input
N/A
C
Output Data
Clock
Input
N/A
D
0
- D
17
Data Input
Input
N/A
Q
0
- Q
17
Data Output
Output
N/A
ZQ
Programmable
Impedance
Matching
Input
N/A
Pin Descriptions continued on Page 3.
6.42
2
IDT71T64805, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 4
Advance Information
Commercial Temperature Range
Pin Definitions continued
Symbol
TMS
TDI
TCK
TDO
V
REF
Pin Function
Test Mode
Select
Test Data
Input
Test Clock
Test Data
Output
Input
Reference
Voltage
Core Power
Supply
I/O Power
Supply
Ground
I/O
Input
Input
Input
Output
Input
Active
N/A
N/A
N/A
N/A
Description
Gives input command for TAP controller; sample d rising edge of TCK.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising
edge of TCK, while test outputs are driven from falling edge of TCK.
Serial output of registers placed between TDI and TDO. This output is active dpending on
state of TAP controller.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs,
nominally V
DDQ
/2 but may be adjusted to improve system noise margins.
Power supply inputs to the core of the device. Should b e connected to 2.5V power supply.
Power supply inputs for the outputs of the device. Should be connected to 1.5V power
supply.
Ground for the core of the device. Should be connected to ground of the system.
5284 tbl 02b
N/A
V
DD
V
DDQ
V
SS
N/A
N/A
N/A
N/A
N/A
N/A
Introduction
Functional Overview
The IDT71T64805 is a synchronous pipelined Burst SRAM
equipped with both a Read port and a Write Port. The Read port is
dedicated to Read operations and the Write Port is dedicated to Write
operations. Data flows into the SRAM through the Write port and out
through the Read port. The IDT71T64805 multiplexes the address
inputs in order to minimize the number of address pins required. By
having separate Read and Write ports, the IDT71T64805 completely
eliminates the need to “turn-around” the data bus and avoids any
possible data contention, thereby simplifying system design. Each ac-
cess consists of four 18-bit data transfers in two clock cycles.
Accesses for both ports are initiated on the positive input clock (K).
All synchronous input timing is referenced from the rising edge of the
input clocks (K and
K)
and all output timing is referenced to the output
clocks (C and
C
or K and
K
when in single clock mode).
All synchronous data inputs (D
IN[17:0]
) pass through input regis-
ters controlled by the input clocks (K and
K).
All synchronous data
outputs (D
OUT[17:0]
) pass through output registers controlled by the
rising edge of the output clocks (C and
C
or K and
K
when in single
clock mode).
All synchronous control (RPE,
WPE, BW
0
,
BW
1
) inputs pass
through input registers controlled by the rising edge of the input clocks
(K and
K,
C and
C
).
Read Operations
The IDT71T64805 is organized internally as a 128K x 72 SRAM.
Accesses are completed in a burst of four sequential 18-bit data words.
Read operations are initiated by asserting
RPE
active at the rising
edge of the positive input clock (K). The address presented to Address
inputs are stored in the Read address register. Following the next K
clock rise the corresponding lowest order 18-bit word of data is driven
onto the D
OUT[17:0]
using C as the output timing reference. On the
subsequent rising edge of
C
the next 18-bit data word is driven onto
the D
OUT[17:0]
. This process continues until all four 18-bit data words
have been driven out onto D
OUT[17:0]
. The requested data will be
valid 2.4ns from the rising edge of the output clock (C or
C,
166 MHz
device). In order to maintain the internal logic, each read access must
be allowed to complete. Each Read access consists of four 18-bit data
words and takes two clock cycles to complete. Therefore, Read ac-
cesses to the device can not be initiated on two consecutive K clock
rises. The internal logic of the device will ignore the second Read
request. Read accesses can be initiated on every other K clock rise.
Doing so will pipeline the data flow such that data is transferred out of
the device on every rising edge of the output clocks (C and
C
or K and
K
when in single clock mode).
When the Read port is deselected, the IDT71T64805 will first com-
plete the pending read transactions. Synchronous internal circuitry will
automatically three-state the outputs following the next rising edge of
the negative output clock (C). This will allow for a seamless transition
between devices without the insertion of wait states in a depth ex-
panded memory.
Write Operations
Write operations are initiated by asserting
WPE
active at the rising
edge of the positive input clock (K). On the following K clock rise the
data presented to D
IN[17:0]
is latched and stored into the lower 18-bit
Write Data register provided
BW
[1:0]
are both asserted active. On the
subsequent rising edge of the negative input clock (K) the information
presented to D
IN[17:0]
is also stored into the Write Data Register pro-
vided
BW
[1:0]
are both asserted active. This process continues for one
more cycle until four 18-bit words (a total of 72 bits) of data are stored
in the SRAM. The 72 bits of data are then written into the memory array
at the specified location. Therefore, Write accesses to the device can
not be initiated on two consecutive K clock rises. The internal logic of
the device will ignore the second Write request. Write accesses can be
initiated on every other rising edge of the positive clock (K). Doing so
will pipeline the data flow such that 18-bits of data can be transferred
into the device on every rising edge of the input clocks (K and
K).
When deselected, the write port will ignore all inputs after the pend-
ing Write operations have been completed.
Introduction continued on Page 4.
6.42
3
IDT71T64805, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 4
Advance Information
Commercial Temperature Range
Introduction
continued
Byte Write Operations
Byte Write operations are supported by the IDT71T64805. A write
operation is initiated as described in the Write Operation section above.
The bytes that are written are determined by
BW
0
and
BW
1
which are
sampled with each set of 18-bit data word. Asserting the appropriate
Byte Write Enable input during the data portion of a write will allow the
data being presented to be latched and written into the device. De-
asserting the Byte Write Enable input during the data portion of a write
will allow the data stored in the device for that byte to remain unaltered.
This feature can be used to simplify READ/MODIFY/WRITE opera-
tions to a Byte Write operation.
Single Clock Mode
The IDT71T64805 can be used with a single clock that controls
both the input and output registers. In this mode the device will recog-
nize only a single pair of input clocks (K and
K)
that control both the
input and output registers. This operation is identical to the operation if
the device had zero skew between the K/K and C/C clocks. All timing
parameters remain the same in this mode. To use this mode of opera-
tion, the user must tie C and
C
HIGH at power on. This function is a
strap option and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the IDT71T64805 operate completely
independently of one another. Since each port latches the address
inputs on different clock edges, the user can Read or Write to any
location, regardless of the transaction on the other port. If the ports
access the same location at the same time, the SRAM will deliver the
most recent information associated with the specified address location.
This includes forwarding data from a Write cycle that was initiated on
the previous K clock rise.
Read access and Write access operations must be scheduled such
that one transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports were deselected, the Read
port will take priority. If a Read was initiated on the previous cycle, the
Write port will assume priority (since Read operations can not be initi-
ated on consecutive cycles). If a Write was initiated on the previous
cycle, the Read port will assume priority (since Write operations can
not be initiated on consecutive cycles). Therefore, asserting both port
selects active from a deselected state will result in alternating Read/
Write operations being initiated, with the first access being a Read.
Depth Expansion
The IDT71T64805 has a Port Enable input for each port. This
allows for easy depth expansion. Both Port Enables are sampled on
the rising edge of the positive input clock only (K). Each port enable
input can disable the specified port. Disabling a port will not affect the
other port. All pending transactions (Read and Write) will be completed
prior to the device being disabled.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and V
SS
to allow the SRAM to adjust its output driver imped-
ance. The value of RQ must be 5X the value of the intended line
impedance driven by the SRAM, The allowable range of RQ to guar-
antee impedance matching with a tolerance of +/-10% is
between 175
Ω
and 350
Ω
, with V
DDQ
=1.5V. The output impedance is
adjusted every 1024 cycles to adjust for drifts in supply voltage and
temperature.
6.42
4
IDT71T64805, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 4
Advance Information
Commercial Temperature Range
Functional Block Diagram
D
[17:0]
18
Write
Reg
Write
Reg
Write
Reg
Write
Reg
Write Add. Decode
Read Add. Decode
A
17
Address
Register
Address
Register
17
A
128K x 18 Array
128K x 18 Array
128K x 18 Array
128K x 18 Array
K
K
CLK
Gen.
Control
Logic
RPE
C
Read Data Reg.
72
Control
Logic
C
36
Reg.
Reg.
18
Q
[17:0]
V
REF
WPE
BW
[0:1]
36
Reg.
18
5824 drw 01
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Ambient
Temperature
(1)
0°C to +70°C
V
SS,
V
SSQ
OV
V
DD
2.5 ± 100mV
V
DDQ
1.4V to 1.9V
5284 tbl 03
Recommended DC Operating
Conditions
Symbol
V
DD
V
DDQ
V
SS
V
IH
V
IL
Parameter
Power Supply
Voltage
I/O Supply
Voltage
Ground
Input High
Voltage
Input Low Voltage
Min.
2.4
1.4
0
V
REF
+0.1
–0.3
(1)
Typ.
2.5
1.5
0
–
–
Max.
2.6
1.9
0
V
DDQ
+0.3
V
REF
–0.1
Unit
V
V
V
V
V
5284 tbl 04
NOTE:
1. T
A
is the “instant on” case temperature.
NOTE:
1. minimum voltage equals -2.0V for pulse duration less than 20ns.
6.42
5
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