HCPL3700M — AC/DC to Logic Interface Optocoupler
November 2015
HCPL3700M
AC/DC to Logic Interface Optocoupler
Features
AC or DC Input
Programmable Sense Voltage
Logic Level Compatibility
Threshold Guaranteed Over Temperature
(0°C to 70°C)
• Safety and Regulatory Approvals
– UL1577, 5,000 VAC
RMS
for 1 Minute
– DIN EN/IEC60747-5-5
•
•
•
•
Description
The HCPL3700M voltage/current threshold detection
optocoupler consists of an AlGaAs LED connected to a
threshold sensing input buffer IC which are optically cou-
pled to a high gain darlington output. The input buffer
chip is capable of controlling threshold levels over a wide
range of input voltages with a single resistor. The output
is TTL and CMOS compatible.
Applications
•
•
•
•
•
•
Low Voltage Detection
5 V to 240 V AC/DC Voltage Sensing
Relay Contact Monitor
Current Sensing
Microprocessor Interface
Industrial Controls
Schematics
AC
DC+
DC-
AC
1
2
3
4
8
7
6
5
V
CC
Package Outlines
8
NC
1
V
O
GND
8
1
8
1
Figure 2. Package Outlines
AC/DC
POWER
R
X
HCPL3700M
LOGIC
TRUTH TABLE
(Positive Logic)
Input
H
GND 1
GND 2
Output
L
H
L
Figure 1. Schematic
A 0.1μF bypass capacitor must be connected
between pins 8 and 5.
©2015 Fairchild Semiconductor Corporation
HCPL3700M Rev. 1.0
www.fairchildsemi.com
HCPL3700M — AC/DC to Logic Interface Optocoupler
Safety and Insulation Ratings
As per DIN EN/IEC 60747-5-5, this optocoupler is suitable for “safe electrical insulation” only within the safety limit
data. Compliance with the safety ratings shall be ensured by means of protective circuits.
Parameter
< 150 V
RMS
Installation Classifications per DIN VDE
0110/1.89 Table 1, For Rated Mains Voltage
< 300 V
RMS
< 450 V
RMS
< 600 V
RMS
< 1000 V
RMS
(Option TV)
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Comparative Tracking Index
Characteristics
I–IV
I–IV
I–III
I–III
I–III
40/85/21
2
175
Symbol
V
PR
V
IORM
V
IOTM
Parameter
Input-to-Output Test Voltage, Method A, V
IORM
x 1.6 = V
PR
,
Type and Sample Test with t
m
= 10 s, Partial Discharge < 5 pC
Input-to-Output Test Voltage, Method B, V
IORM
x 1.875 = V
PR
,
100% Production Test with t
m
= 1 s, Partial Discharge < 5 pC
Maximum Working Insulation Voltage
Highest Allowable Over-Voltage
External Creepage
External Clearance
External Clearance (for Option TV, 0.4" Lead Spacing)
Value
2,262
2,651
1,414
6,000
≥
8
≥
7.4
≥
10.16
≥
0.5
150
25
250
> 10
9
Unit
V
peak
V
peak
V
peak
V
peak
mm
mm
mm
mm
°C
mA
mW
Ω
DTI
T
S
I
S,INPUT
P
S,OUTPUT
R
IO
Distance Through Insulation (Insulation Thickness)
Case Temperature
(1)
Input Current
(1)
Output Power (Duty Factor
≤
2.7%)
(1)
Insulation Resistance at T
S
, V
IO
= 500 V
(1)
Note:
1. Safety limit value - maximum values allowed in the event of a failure.
©2015 Fairchild Semiconductor Corporation
HCPL3700M Rev. 1.0
www.fairchildsemi.com
2
HCPL3700M — AC/DC to Logic Interface Optocoupler
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. T
A
= 25°C unless otherwise specified.
Symbol
T
STG
T
OPR
T
J
T
SOL
P
T
EMITTER
Storage Temperature
Operating Temperature
Junction Temperature
Lead Solder Temperature
Parameter
Value
-40 to +125
-40 to +85
-40 to +125
260 for 10 sec
305
Unit
°C
°C
°C
°C
mW
Total Package Power Dissipation
(2)
Average
50
140
500
-0.5
230
30
-0.5 to 20
-0.5 to 20
210
V
mW
mA
V
V
mW
mA
I
IN
V
IN
P
IN
I
O
V
CC
V
O
P
O
Input Current
Input Voltage (Pins 2-3)
Input Power Dissipation
(3)
Output Current (Average)
(4)
Supply Voltage (Pins 8-5)
Output Voltage (Pins 6-5)
Output Power Dissipation
(5)
Surge, 3 ms, 120 Hz Pulse Rate
Transient, 10
μs,
120 Hz Pulse Rate
DETECTOR
Notes:
2. Derate linearly above 70°C free-air temperature at a rate of 2.5 mW/°C.
3. Derate linearly above 70°C free-air temperature at a rate of 1.8 mW/°C.
4. Derate linearly above 70°C free-air temperature at a rate of 0.6 mA/°C.
5. Derate linearly above 70°C free-air temperature at a rate of 1.9 mW/°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
T
A
f
Supply Voltage
Parameter
Ambient Operating Temperature
Operating Frequency
Min.
2
0
0
Max.
18
70
4
Unit
V
°C
kHz
©2015 Fairchild Semiconductor Corporation
HCPL3700M Rev. 1.0
www.fairchildsemi.com
3
HCPL3700M — AC/DC to Logic Interface Optocoupler
Electrical Characteristics
(T
A
= 0°C to 70°C Unless otherwise specified)
Symbol
I
TH+
I
TH-
V
TH+
Parameter
Input Threshold Current
Test Conditions
V
IN
= V
TH+
, V
CC
= 4.5 V
V
O
= 0.4 V, I
O
≥
4.2 mA
(6)
V
IN
= V
2
- V
3
(Pins 1 & 4 Open)
V
CC
= 4.5 V, V
O
= 0.4 V
(6)
I
O
≥
4.2 mA
Min.
1.96
1.00
3.35
Typ.
2.40
1.20
3.80
Max.
3.11
1.62
4.05
Unit
mA
V
V
TH-
Input Threshold Voltage
V
TH+
DC
(Pins 2, 3) V
IN
= V
2
- V
3
(Pins 1 & 4 Open)
V
CC
= 4.5 V, V
O
= 2.4 V
(6)
I
O
≥
100 µA
lV
IN
= V
1
- V
4
l (Pins 2 & 3 Open)
V
CC
= 4.5 V, V
O
= 0.4 V
(6)
I
O
≥
4.2 mA
2.01
2.50
2.86
V
4.23
5.00
5.50
V
V
TH-
I
HYS
V
HYS
V
IHC1
V
IHC2
V
IHC3
V
ILC
I
IN
V
D1,2
V
D3,4
V
OL
I
OH
I
CCL
I
CCH
C
IN
Input Current
Bridge Diode
Forward Voltage
Hysteresis
AC
(Pins 1, 4) lV
IN
= lV
1
- V
4
l (Pins 2 & 3 Open)
V
CC
= 4.5 V, V
O
= 2.4 V
(6)
I
O
≤
100 µA
I
HYS
= I
TH+
- I
TH-
V
HYS
= V
TH+
- V
TH-
V
IHC1
= V
2
- V
3
, V
3
= GND,
I
IN
= 10 mA,
Pins 1 & 4 connected to Pin 3
Input Clamp Voltage
V
IHC2
= lV
1
- V
4
l, lI
IN
l = 10 mA
(Pins 2 & 3 Open)
V
IHC3
= V
2
- V
3
, V
3
= GND,
I
IN
= 15 mA (Pins 1 & 4 Open)
V
ILC
= V
2
- V
3
, V
3
= GND,
I
IN
= -10 mA
V
IN
= V
2
- V
3
= 5.0 V
(Pins 1 & 4 Open)
I
IN
= 3 mA
I
IN
= 3 mA
V
CC
= 4.5 V, I
OL
=
4.2 mA
(6)
V
OH
= V
CC
= 18 V
(6)
V
2
- V
3
= 5.0 V, V
O
= Open,
V
CC
= 5 V
V
CC
= 18 V, V
O
= Open
f = 1 MHz, V
IN
= 0 V
(Pins 2 & 3, Pins 1 & 4 Open)
2.87
3.70
1.2
1.3
4.20
V
mA
V
5.4
6.1
6.3
7.0
12.5
-0.75
6.6
7.3
13.4
V
V
V
V
3.0
3.7
0.65
0.65
0.04
4.4
mA
V
V
Logic LOW Output Voltage
Logic HIGH Output Current
Logic LOW Supply Current
Logic HIGH Supply Current
Input Capacitance
0.40
100
V
µA
mA
µA
pF
1.0
0.01
50
4
4
Note:
6. Logic LOW output level at pin 6 occurs when V
IN
≥
V
TH+
and when V
IN
> V
TH-
once V
IN
exceeds V
TH+
.
Logic HIGH output level at pin 6 occurs when V
IN
≤
V
TH-
and when V
IN
< V
TH+
once decreases below V
TH-.
©2015 Fairchild Semiconductor Corporation
HCPL3700M Rev. 1.0
www.fairchildsemi.com
4
HCPL3700M — AC/DC to Logic Interface Optocoupler
Switching Characteristics
(T
A
= 25°C, V
CC
= 5 V unless otherwise specified)
Symbol
t
PHL
t
PLH
t
R
t
F
|CM
H
|
|CM
L
|
Parameter
Propagation Delay Time
(to Output Low Level)
Propagation Delay Time
(to Output High Level)
Output Rise Time (10–90%)
Output Fall Time (90–10%)
Common Mode Transient
Immunity (at Output High Level)
Common Mode Transient
Immunity (at Output Low Level)
Test Conditions
R
L
= 4.7 kΩ, C
L
= 30 pF
(7)
R
L
= 4.7 kΩ, C
L
= 30 pF
(7)
R
L
= 4.7 kΩ, C
L
= 30 pF
R
L
= 4.7 kΩ, C
L
= 30 pF
I
IN
= 0 mA, R
L
= 4.7 kΩ,
V
O min
= 2.0 V, V
CM
= 1400 V
(8)(9)
I
IN
= 3.11 mA, R
L
= 4.7 kΩ,
V
O max
= 0.8 V, V
CM
= 1400 V
(8)(9)
Min.
Typ.
6.0
25.0
45
0.5
4000
600
Max.
15
40
Unit
µs
µs
µs
µs
V/µs
V/µs
Isolation Characteristics
(T
A
= 25°C unless otherwise specified.)
Symbol
V
ISO
R
I-O
C
I-O
Parameter
Withstand Isolation Voltage
Resistance (Input to Output)
Capacitance (Input to Output)
Test Conditions
RH
≤
50%, I
I-O
≤
10 µA
t = 1 minute, f = 50 Hz
(10)(11)
V
IO
= 500 V
DC(10)
f = 1 MHz, V
IO
= 0 V
DC
Min.
5000
Typ.
Max.
Unit
VAC
RMS
10
12
0.6
Ω
pF
Notes:
7. T
PHL
propagation delay is measured from the 2.5 V level of the leading edge of a 5.0 V input pulse (1
μs
rise time)
to the 1.5 V level on the leading edge of the output pulse. T
PLH
propagation delay is measured on the trailing edges
of the input and output pulse. (Refer to Fig. 9)
8. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV
cm
/dt on the leading edge
of the common mode pulse signal V
CM
, to assure that the output will remain in a logic high state (i.e., V
O
> 2.0 V).
Common mode transient immunity in logic low level is the maximum tolerable (negative) dV
cm
/dt on the trailing edge
of the common mode pulse signal, V
CM
, to assure that the output will remain in a logic low state (i.e., V
O
< 0.8 V).
Refer to Fig. 10.
9. In applications where dV
cm
/dt may exceed 50,000 V/μs (Such as static discharge), a series resistor, R
CC
, should be
included to protect the detector chip from destructive surge currents. The recommended value for R
CC
is 240 V per
volt of allowable drop in V
CC
(between pin 8 and V
CC
) with a minimum value of 240
Ω.
10. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted
together.
11. The 5000 VAC
RMS
/1 min. capability is validated by a 6000 VAC
RMS
/1 sec. dielectric voltage withstand test.
©2015 Fairchild Semiconductor Corporation
HCPL3700M Rev. 1.0
www.fairchildsemi.com
5
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