FAST CMOS
BUS INTERFACE
LATCHES
Integrated Device Technology, Inc.
IDT54/74FCT841AT/BT/CT/DT
FEATURES:
• Common features:
– Low input and output leakage
≤1µA
(max.)
– CMOS power levels
– True TTL input and output compatibility
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for FCT841T:
– A, B, C and D speed grades
– High drive outputs (-15mA I
OH
, 48mA I
OL
)
– Power off disable outputs permit “live insertion”
DESCRIPTION:
The FCT8xxT series is built using an advanced dual metal
CMOS technology.
The FCT8xxT bus interface latches are designed to elimi-
nate the extra packages required to buffer existing latches
and provide extra data width for wider address/data paths or
buses carrying parity. The FCT841T are buffered, 10-bit wide
versions of the popular FCT373T function. They are ideal for
use as an output port requiring high I
OL
/I
OH
.
All of the FCT8xxT high-performance interface family can
drive large capacitive loads, while providing low-capacitance
bus loading at both inputs and outputs. All inputs have clamp
diodes to ground and all outputs are designed for low-capaci-
tance bus loading in high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D
0
D
1
D
2
D
3
D
4
D
5
D
8
D
9
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
LE
OE
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
8
Y
9
2571 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
JUNE 1996
2571/6
6.22
1
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
GND
1
2
3
4 P24-1
5 D24-1
SO24-2
6
SO24-7
7
SO24-8
8
&
9 E24-1
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
LE
D
2
D
3
D
4
NC
D
5
D
6
D
7
4 3 2
1 28 27 26
25
5
24
6
23
7
8
22
L28-1
9
21
20
10
19
11
1213 14 15 16 17 18
D
1
D
0
OE
NC
V
CC
Y
0
Y
1
INDEX
Y
2
Y
3
Y
4
NC
Y
5
Y
6
Y
7
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
2571 drw 02
D
8
D
9
GND
NC
LE
Y
9
Y
8
LCC
TOP VIEW
2571 drw 03
PIN DESCRIPTION
Name
D
I
LE
I/O
I
I
Description
The latch data inputs.
The latch enable input. The latches are
transparent when LE is HIGH. Input data
is latched on the HIGH-to-LOW
transition.
The 3-state latch outputs.
The output enable control. When
OE
is
LOW, the outputs are enabled. When
OE
is HIGH, the outputs V I are in high-
impedance (off) state.
2571 tbl 01
FUNCTION TABLE
(1)
Inputs
LE
H
H
L
H
H
L
Internal Output
Q
I
Y
I
L
H
NC
L
H
NC
Z
Z
Z
L
H
NC
OE
H
H
H
L
L
L
D
I
L
H
X
L
H
X
Function
High Z
High Z
Latched (High Z)
Transparent
Transparent
Latched
Y
I
O
I
OE
NOTE:
2571 tbl 02
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, Z = High Impedance
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
V
TERM(2)
Terminal Voltage
–0.5 to +7.0
with Respect to
GND
V
TERM(3)
Terminal Voltage
–0.5 to
with Respect to
V
CC
+0.5
GND
T
A
Operating
0 to +70
Temperature
T
BIAS
Temperature
–55 to +125
Under Bias
T
STG
Storage
–55 to +125
Temperature
P
T
Power Dissipation
0.5
I
OUT
DC Output
Current
–60 to +120
Military
–0.5 to +7.0
Unit
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max. Unit
10
pF
12
pF
2571 lnk 04
–0.5 to
V
CC
+0.5
–55 to +125
–65 to +135
–65 to +150
0.5
–60 to +120
V
°
C
°
C
°
C
W
mA
NOTE:
1. This parameter is measured at characterization but not tested.
NOTES:
2571 lnk 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
6.22
2
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
I
I
V
IK
V
H
I
CC
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(3-State Output pins)
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min., I
IN
= –18mA
—
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
V
CC
= Max., V
I
= V
CC
(Max.)
Min.
2.0
—
—
—
—
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
200
0.01
Max.
—
0.8
±1
±1
±1
±1
±1
–1.2
—
1
Unit
V
V
µA
µA
µA
V
mV
mA
2571 lnk 05
V
CC
= Max., V
IN
= GND or V
CC
OUTPUT DRIVE CHARACTERISTICS FOR FCT841T
Symbol
V
OH
Parameter
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Min.
I
OH
= –6mA MIL.
V
IN
= V
IH
or V
IL
I
OH
= –8mA COM'L.
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
V
CC
= Min.
I
OL
= 32mA MIL.
V
IN
= V
IH
or V
IL
I
OL
= 48mA COM'L.
V
CC
= Max., V
O
= GND
(3)
V
CC
= 0V, V
IN
or V
O
≤
4.5V
Min.
2.4
2.0
—
–60
—
Typ.
(2)
3.3
3.0
0.3
–120
—
Max.
—
—
0.5
–225
Unit
V
V
V
mA
V
OL
I
OS
I
OFF
Output LOW Voltage
Short Circuit Current
Input/Output Power Off Leakage
(5)
±
1
µ
A
2571 lnk 06
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is
±5µA
at T
A
= –55°C.
5. This parameter is guaranteed but not tested.
6.22
3
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
= GND
LE = V
CC
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
OE
=
GND
LE = V
CC
One Bit Toggling
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
OE
=
GND
LE = V
CC
Eight Bits Toggling
Min.
—
—
Typ.
(2)
0.5
0.15
Max.
2.0
0.25
Unit
mA
mA/
MHz
V
IN
= V
CC
V
IN
= GND
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4
V
IN
= GND
—
1.5
3.5
mA
—
1.8
4.5
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4
V
IN
= GND
—
3.0
6.0
(5)
—
5.0
14.0
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP/
2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2571 tbl 07
6.22
4
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841AT
Com'l.
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
D
I
to Y
I
(LE = HIGH)
FCT841BT
Mil.
Com'l.
Max.
6.5
13.0
8.0
15.5
8.0
14.0
6.0
7.0
—
—
—
10.0
15.0
13.0
20.0
13.0
25.0
9.0
10.0
—
—
—
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
4.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
4.0
Mil.
Min.
(2)
Max.
7.5
15.0
10.5
18.0
8.5
15.0
6.5
7.5
—
—
—
ns
ns
ns
2571 tbl 08
t
PLH
t
PHL
Propagation Delay
LE to Y
I
t
PZH
t
PZL
Output Enable Time
OE
to Y
I
t
PHZ
t
PLZ
Output Disable Time
OE
to Y
I
t
SU
t
H
t
W
Data to LE Set-up Time
Data to LE Hold Time
LE Pulse Width HIGH
(3)
Conditions
(1)
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(4)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(4)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(4)
R
L
= 500Ω
C
L
= 5pF
(4)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
Min.
(2)
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
4.0
Max. Min.
(2)
9.0
13.0
12.0
16.0
11.5
23.0
7.0
8.0
—
—
—
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
3.0
5.0
Max. Min.
(2)
Unit
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
4. These conditions are guaranteed but not tested.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841CT
Com'l.
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
D
I
to Y
I
(LE = HIGH)
FCT841DT
Mil.
Com'l.
Max.
4.2
8.0
4.0
8.0
4.8
9.0
4.0
4.0
—
—
—
6.3
15.0
6.8
16.0
7.3
13.0
6.0
6.3
—
—
—
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.0
3.0
—
—
—
—
—
—
—
—
—
—
—
Mil.
Min.
(2)
Max.
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
2571 tbl 09
t
PLH
t
PHL
Propagation Delay
LE to Y
I
t
PZH
t
PZL
Output Enable Time
OE
to Y
I
t
PHZ
t
PLZ
Output Disable Time
OE
to Y
I
t
SU
t
H
t
W
Data to LE Set-up Time
Data to LE Hold Time
LE Pulse Width HIGH
(3)
Conditions
(1)
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(4)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(4)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(4)
R
L
= 500Ω
C
L
= 5pF
(4)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
Min.
(2)
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
4.0
Max. Min.
(2)
5.5
13.0
6.4
15.0
6.5
12.0
5.7
6.0
—
—
—
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
4.0
Max. Min.
(2)
Unit
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
4. These conditions are guaranteed but not tested.
6.22
5
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