MK2745-24
DVD/MPEG C
LOCK
S
OURCE
Description
The MK2745-24 is a low-cost, low-jitter,
high-performance clock synthesizer for DVD and other
MPEG 2-based applications. Using analog
Phase-Locked Loop (PLL) techniques, the device
accepts a 27 MHz fundamental mode crystal or clock
input to produce multiple audio output clocks, a
processor clock, and two 27 MHz clocks. The audio
clocks are frequency-locked to the 27 MHz using our
patented zero ppm error techniques. This allows audio
and video to track exactly, thereby eliminating the need
for large buffer memory.
ICS manufactures a large variety of DVD, Set-top Box,
and multiimedia clock synthesizers for all applications.
Consult ICS to eliminate crystals and oscillators from
your board.
Features
•
Packaged in a 16-pin narrow (150 mil) SOIC
•
Ideal for AuraVision’s notebook DVD solutions
•
Patented zero ppm audio clock error for exact audio
clock sampling rates, plus 32x and 256x clocks of the
sampling frequencies
•
Selectable audio sampling frequencies support 32,
44.1, and 96 kHz in most DACs
•
•
•
•
•
•
•
•
27 MHz fundamental crystal or clock input
Selectable processor frequencies
Two clocks of 27 MHz
Zero ppm in all clocks
25 mA output drive capability at TTL levels
Advanced, low-power, sub-micron CMOS process
Operating voltage of 3.3 V to 5 V
See also the MK2712 for NTSC/PAL clocks
Block Diagram
VDD
2
CLKA1
FBIN
CLKIN
CLKA2
CLKA3
CLKA4
BANK
A
PLL
/2
CLKB1
CLKB2
S2, S1
2
Control
Logic
CLKB3
CLKB4
BANK
B
2
GND
MDS 2745-24 D
I n t e gra te d C i r c u i t S y s t e m s
●
1
525 Race Stre et, San Jo se, CA 9 5126
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Revision 042904
te l (40 8) 2 97-12 01
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w w w. i c st . c o m
MK2745-24
DVD/MPEG C
LOCK
S
OURCE
Pin Assignment
CLKIN
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBIN
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Feedback Configuration Table
Feedback From
Bank A
Bank B
CLKA1:A4
CLKIN
2XCLKIN
CLKB1:B4
CLKIN/2
CLKIN
16-pin (150 mil) SOIC
Output Clock Mode Select Table
S2
0
0
1
1
S1
0
1
0
1
Clocks A1:A4
Tri-state (high impedance)
Running
Running
Running
Clocks B1:B4
Tri-state (high impedance)
Tri-state (high impedance)
Running
Running
Internet Generation
None
PLL
Buffer only (no zero delay)
PLL
PLL Status
On
On
Off
On
Pin Descriptions
Pin
Number
1
2, 3
4
5
6, 7
8
9
10, 11
12
13
14, 15
16
Pin
Name
CLKIN
CLKA1:A4
VDD
GND
CLKB1:B4
S2
S1
CLKB1:B4
GND
VDD
CLKA1:A4
FBIN
Pin
Type
Input
Output
Power
Power
Output
Input
Input
Output
Power
Power
Output
Input
Pin Description
Clock input. Connect to input clock source.
Clock A bank of four outputs.
Power supply. Connect pin to same voltage as pin 13 (either 3.3 V or 5 V).
Connect to ground.
Clock B bank of four outputs. These are low skew divide by two of bank A.
Select input 2. Selects mode for outputs per table above.
Select input 1. Selects mode for outputs per table above.
Clock B bank of four outputs. These are low skew divide by two of bank A.
Connect to ground.
Power supply. Connect pin to same voltage as pin 4 (either 3.3 V or 5 V).
Clock A bank of four outputs.
Feedback input. Determines outputs per table above.
MDS 2745-24 D
In te grated Circuit Systems
●
2
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 042904
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
MK2745-24
DVD/MPEG C
LOCK
S
OURCE
External Components
The MK2745-24 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1µF should be connected between VDD and GND, as close to the part as possible. A 33Ω
series terminating resistor should be used on each clock output to reduce reflections.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2745-24. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature (Commercial)
Ambient Operating Temperature (Industrial)
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70°C
-40 to +85°C
-65 to +150°C
125°C
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
Max.
+70
+5.5
Units
°C
V
MDS 2745-24 D
In te grated Circuit Systems
●
3
525 Ra ce Street, San Jose, CA 9512 6
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Revision 042904
tel (4 08) 297-1 201
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w w w. i c s t . c o m
MK2745-24
DVD/MPEG C
LOCK
S
OURCE
DC Electrical Characteristics
VDD=3.3 V ±10%,
Temp 0 to +70°
/-40
to +85° C
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Operating Supply Current
100 MHz, CLKIN
Short Circuit Current
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
IDD
I
OS
C
IN
Conditions
CLKIN pin only
CLKIN pin only
Min.
3.0
(VDD/2)+1
2
Typ.
VDD/2
VDD/2
Max.
5.5
(VDD/2)-1
0.8
Units
V
V
V
V
V
V
V
V
mA
mA
pF
I
OH
= -18 mA
I
OL
= 18 mA
I
OH
= -5 mA
No Load
S1=S2=1
Each output
S1, S1, FBIN
2.4
0.4
VDD-0.4
44
± 65
7
AC Electrical Characteristics
VDD = 3.3V ±10%,
Temp 0 to +70°/ -40 to +85° C
Parameter
Input Frequency
Output Frequency
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Device-to-Device skew, equally
loaded
Output-to-Output skew, equally
loaded
Maximum Absolute Jitter
Cycle-to-Cycle Jitter
Symbol
Conditions
FBIN to CLKA1
S1=S2=1
FBIN to CLKA1
S1=S2=1
Min.
20
20
Typ.
Max. Units
160
160
1.5
1.5
MHz
MHz
ns
ns
%
ps
ps
ps
400
400
ps
ps
t
OR
t
OF
0.8 to 2.0 V, C
L
=30 pF
0.8 to 2.0 V, C
L
=30 pF
at 1.4V
Rising edges at VDD/2
Rising edges at VDD/2
300
30 pF loads
66.67 MHz outputs
15 pF loads
66.67 MHz outputs
40
50
60
700
200
MDS 2745-24 D
In te grated Circuit Systems
●
4
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 042904
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
MK2745-24
DVD/MPEG C
LOCK
S
OURCE
Parameter
Skew from Output Bank A to
Output Bank B
Delay CLKIN Rising Edge to
FBIN Rising Edge
PLL Lock Time
Symbol
Conditions
All outputs equally
loaded
Measured at VDD/2
Min.
Typ.
Max. Units
400
±250
1
ps
ps
ms
t
LOCK
Stable power supply,
valid clocks on CLKIN,
FBIN
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
120
115
105
58
Max. Units
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to Case
MDS 2745-24 D
In te grated Circuit Systems
●
5
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 042904
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
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