www.cadeka.com
TMC3033
Triple Video D/A Converter
10 bit, 80 Msps
Features
•
•
•
•
•
•
10-bit resolution
80, 50, and 30 megapixels per second
Sync and blank controls
Sync on green D/A output
1.0V p-p video into 37.5
Ω
or 75
Ω
load
Enhancement of ADV7122
– Internal bandgap voltage reference
– Double-buffered data for low distortion
• TTL-compatible inputs
• Low glitch energy
• Single +3.3 Volt
±
5% power supply
Description
The TMC3033 is a high-speed triple 10-bit D/A converter
especially suited for video and graphics applications.
It offers 10-bit resolution, TTL-compatible inputs, low
power consumption, and requires only a single +3.3 Volt
±
5% power supply. It has single-ended current outputs,
SYNC and BLANK control inputs, and a separate current
source for adding sync pulses to the Green D/A converter
output. It is ideal for generating analog RGB from digital
RGB and driving computer display and video monitors.
Three speed grades are available: 30, 50, and 80 Msps.
The TMC3033 triple D/A converter is available in a 44-lead
plastic J-leaded PLCC and 48-lead plastic LQFP package.
It is fabricated on a sub-micron CMOS process with perfor-
mance guaranteed from 0
°
C to 70
°
C.
Applications
• Video signal conversion
– RGB
– YC
B
C
R
– Composite, Y, C
• Multimedia systems
• Image processing
• True-color graphics systems (1 billion colors)
• Broadcast television equipment
• High-Definition Television (HDTV) equipment
• Direct digital synthesis
Block Diagram
SYNC
BLANK
10
10 bit
D/A Converter
G
9-0
IO
G
B
9-0
10
10 bit
D/A Converter
IO
B
R
9-0
CLK
10
10 bit
D/A Converter
IO
R
COMP
R
REF
V
REF
65-3003-01
+1.235V
Ref
Rev. 1.0.0
TMC3033
PRODUCT SPECIFICATION
Functional Description
The TMC3033 is a low-cost triple 10-bit CMOS D/A
converter designed to directly drive computer CRT displays
and video transmission lines at pixel rates of up to 80 Msps.
It comprises three identical 10-bit D/A converters with
registered data inputs, common clock, and internal voltage
reference. An independent current source allows sync to be
added to the green D/A converter output.
D/A Outputs
Each D/A output is a current source. To obtain a voltage out-
put a resistor must be connected to ground. Output voltage of
the D/A converters depends upon this resistor, the reference
voltage, and the value of the gain-setting resistor connected
between R
REF
and GND.
Normally, a source termination resistor of 75 Ohms is con-
nected between the D/A current output pin and GND near
the D/A converter. A 75 Ohm coaxial cable may then be con-
nected with another 75 Ohm termination resistor at the far
end of the cable. This “double termination” presents the D/A
converter with a net resistive load of 37.5 Ohms.
The TMC3033 may also be operated with a single 75 Ohm
terminating resistor. To lower the output voltage swing to the
desired range, the value of the resistor on R
REF
should be
increased.
Digital Inputs
All digital inputs are TTL-compatible. Data are registered on
the rising edge of the CLK signal. The analog output
changes t
DO
after the rising edge of CLK. There is one stage
of pipeline delay on the chip. The guaranteed clock rates of
the TMC3033 are 80, 50, and 30 MHz.
SYNC and BLANK
SYNC and BLANK inputs control the output level
(Figure 1 and Table 1) of the D/A converters during CRT
retrace intervals. BLANK forces the D/A outputs to the
blanking level while SYNC turns off a separate current
source which is connected to the green D/A converter. This
connection adds a 40 IRE sync pulse to the D/A output and
brings that D/A output to 0.0 Volts during the sync tip.
SYNC and BLANK are registered on the rising edge of
CLK.
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = HIGH, the D/A inputs are added to a pedestal
which offsets the current output. If BLANK = LOW, data
inputs and the pedestal are disabled.
Voltage Reference
The TMC3033 has an internal bandgap voltage reference
of +1.235 Volts. An external voltage reference may be
connected to the V
REF
pin, overriding the internal voltage
reference. All three D/A converters are driven from the same
reference.
A 0.1
µ
F capacitor must be connected between the COMP
pin and V
DD
to stabilize internal bias circuitry and ensure
low-noise operation.
Power and Ground
The TMC3033 D/A converter requires a single +3.3 Volt
power supply. The analog (V
DD
) power supply voltage
should be decoupled to GND to reduce power supply
induced noise. 0.1
µ
F decoupling capacitors should be placed
as close as possible to the power pins.
The high slew-rate of digital data makes capacitive coupling
to the outputs of any D/A converter a potential problem.
Since the digital signals contain high-frequency components
of the CLK signal, as well as the video output signal, the
resulting data feedthrough often looks like harmonic distor-
tion or reduced signal-to-noise performance. All ground pins
should be connected to a common solid ground plane for
best performance.
data: 660 mV max.
pedestal: 54 mV
sync: 286 mV
65-3003-02
Figure 1. Nominal Output Levels
2
PRODUCT SPECIFICATION
TMC3033
Table 1. Output Voltage versus Input Code, SYNC, and BLANK
V
REF
= 1.235 V, R
REF
= 572
Ω
, R
L
= 37.5
Ω
RGB
9-0
(MSB...LSB)
11 1111 1111
11 1111 1110
11 1111 1101
•
•
10 0000 0000
01 1111 1111
•
•
00 0000 0010
00 0000 0001
00 0000 0000
xx xxxx xxxx
xx xxxx xxxx
Red and Blue D/As
SYNC
X
X
X
•
•
X
X
•
•
X
X
X
X
X
BLANK
1
1
1
•
•
1
1
•
•
1
1
1
0
0
V
OUT
0.7140
0.7134
0.7127
•
•
0.3843
0.3837
•
•
0.0553
0.0546
0.0540
0.0000
0.0000
SYNC
1
1
1
•
•
1
1
•
•
1
1
1
1
0
Green D/A
BLANK
1
1
1
•
•
1
1
•
•
1
1
1
0
0
V
OUT
1.0000
0.9994
0.9987
•
•
0.6703
0.6697
•
•
0.3413
0.3406
0.3400
0.2860
0.0000
Pin Assignments
G
0
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
G
0
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
NC
R
REF
V
REF
COMP
IO
R
IO
G
V
DD
V
DD
IO
B
GND
GND
CLK
48
47
46
45
44
43
42
41
40
39
38
37
6
5
4
3
2
1
44
43
42
41
18
19
20
21
22
23
24
25
26
27
V
DD
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
28
NC
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
NC
13
14
15
16
17
18
19
20
21
22
23
24
G
1
G
2
G
3
G
4
G
5
G
6
G
7
G
8
G
9
BLANK
SYNC
40
7
8
9
10
11
12
13
14
15
16
17
39
38
37
PLCC
TMC3033
36
35
34
33
32
31
30
29
G
1
G
2
G
3
G
4
G
5
G
6
G
7
G
8
G
9
BLANK
SYNC
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
LQFP
TMC3033
36
35
34
33
32
31
30
29
28
27
26
25
R
REF
V
REF
COMP
IO
R
IO
G
OV
DD
V
DD
IO
B
GND
GND
CLOCK
NC
3
TMC3033
PRODUCT SPECIFICATION
Pin Descriptions
Pin Number
Pin Name
CLK
PLCC
29
LQFP
26
Value
TTL
Description
Clock.
The clock input is TTL-compatible and all pixel data
is registered on the rising edge of CLK. It is recommended
that CLK be driven by a dedicated TTL buffer to avoid
reflection induced jitter, overshoot, and undershoot.
Red pixel data inputs.
The Red digital input is TTL-
compatible and registered on the rising edge of CLK.
Clock and Pixel I/O
R
9-0
5, 4, 3, 2, 1,
44, 43, 42,
41, 40
47, 46, 45,
44, 43, 42,
41, 40, 39,
38, 37
TTL
G
9-0
15, 14, 13, 48, 9, 8, 7, 6,
12, 11, 10, 9, 5, 4, 3, 2, 1
8, 7, 6
28, 27, 26,
25, 24, 23,
22, 21, 20,
19
17
23, 22, 21,
20, 19, 18,
17, 16, 15,
14
11
TTL
Green pixel data inputs.
The Green digital input is TTL-
compatible and registered on the rising edge of CLK.
Blue pixel data inputs.
The Blue digital input is TTL-
compatible and registered on the rising edge of CLK.
B
9-0
TTL
Controls
SYNC
TTL
Sync pulse Input.
Bringing SYNC LOW, turns off a 40
IRE (7.62 mA) current source which forms a sync pulse on
the Green D/A converter output. SYNC is registered on the
rising edge of CLK along with pixel data and has the same
pipeline latency as BLANK and pixel data. SYNC does not
override any other data and should be used only during
the blanking interval.
Since this is a single-supply D/A and all signals are
positive-going, sync is added to the bottom of the Green
D/A range. So turning SYNC OFF means turning the
current source ON. When a sync pulse is desired, the
current source is turned OFF. If the system does not
require sync pulses from the Green D/A converter, SYNC
should be connected to GND.
BLANK
16
10
TTL
Blanking Input.
When BLANK is LOW, pixel inputs are
ignored and the D/A converter outputs are driven to the
blanking level. BLANK is registered on the rising edge of
CLK and has the same pipeline latency as SYNC.
Red D/A output.
The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M
compatible levels into doubly-terminated 75 Ohm lines.
Green D/A output.
The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M
compatible levels into doubly-terminated 75 Ohm lines.
Sync pulses may be added to the Green D/A output.
Blue D/A output.
The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M
compatible levels into doubly-terminated 75 Ohm lines.
Video Outputs
IO
R
36
33
0.714 Vp-p
IO
G
35
32
1 V p-p
IO
B
32
29
0.714 Vp-p
4
PRODUCT SPECIFICATION
TMC3033
Pin Descriptions
(continued)
Pin Number
Pin Name
V
REF
PLCC
38
LQFP
35
Value
+1.235 V
Description
Voltage Reference output/input.
An internal voltage
source of +1.235 Volts is output on this pin. An external
+1.235 Volt reference may be applied here which
overrides the internal reference. Decoupling V
REF
to GND
with a 0.1
µ
F ceramic capacitor is required.
Current-setting resistor.
The full-scale output current of
each D/A converter is determined by the value of the
resistor connected between R
REF
and GND. The nominal
value for R
REF
is found from:
R
REF
= 9.1( V
REF
/I
FS
),
but is optimized to be 572
Ω
. I
FS
is the full-scale (white)
output current (in amps) from an output without sync. Sync
current is 0.4 * I
FS
.
D/A full-scale (white) current may also be calculated from:
I
FS
= V
FS
/ R
L
Where V
FS
is the white voltage level and R
L
is the total
resistive load (in ohms) on each D/A converter. V
FS
is the
blank to full-scale voltage.
COMP
37
34
0.1
µ
F
Compensation capacitor.
A 0.1
µ
F ceramic capacitor
must be connected between COMP and V
DD
to stabilize
internal bias circuitry.
Power supply
Ground
Voltage Reference
R
REF
39
36
572
Ω
Power and Ground
V
DD
GND
18, 33, 34
30, 31
12, 30, 31
27, 28
+3.3 V
0.0 V
Equivalent Circuits
V
DD
V
DD
p
Digital
Input
n
OUT
GND
GND
27014C
27013B
n
V
DD
p
Figure 2. Equivalent Digital Input Circuit
Figure 3. Equivalent Analog Output Circuit
5
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
