Philips Semiconductors
Product specification
N-channel logic level TrenchMOS™ transistor
FEATURES
•
’Trench’
technology
• Very low on-state resistance
• Fast switching
• Logic level compatible
g
PSMN010-55D
QUICK REFERENCE DATA
SYMBOL
d
V
DSS
= 55 V
I
D
= 75 A
R
DS(ON)
≤
10.5 mΩ (V
GS
= 10 V)
R
DS(ON)
≤
12 mΩ (V
GS
= 5 V)
s
GENERAL DESCRIPTION
SiliconMAX
products use the latest
Philips Trench technology to
achieve the lowest possible
on-state resistance in each
package at each voltage rating.
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
The PSMN010-55D is supplied in
the SOT428 (Dpak) surface
mounting package.
PINNING
PIN
1
2
3
tab
gate
drain
1
source
DESCRIPTION
SOT428 (DPAK)
tab
2
drain
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Continuous gate-source
voltage
Peak pulsed gate-source
voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 ˚C to 175˚C
T
j
= 25 ˚C to 175˚C; R
GS
= 20 kΩ
T
j
≤
150 ˚C
T
mb
= 25 ˚C; V
GS
= 5 V
T
mb
= 100 ˚C; V
GS
= 5 V
T
mb
= 25 ˚C
T
mb
= 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
±
15
±
20
75
2
57
240
125
175
UNIT
V
V
V
V
A
A
A
W
˚C
1
It is not possible to make connection to pin 2 of the SOT428 package.
2
Continuous current rating limited by package.
October 1999
1
Rev 1.200
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS™ transistor
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
E
AS
I
AS
Non-repetitive avalanche
energy
Non-repetitive avalanche
current
CONDITIONS
Unclamped inductive load, I
AS
= 74 A;
t
p
= 100
µs;
T
j
prior to avalanche = 25˚C;
V
DD
≤
25 V; R
GS
= 50
Ω;
V
GS
= 5 V
MIN.
-
-
PSMN010-55D
MAX.
264
75
UNIT
mJ
A
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
R
th j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
MIN.
-
SOT428 package, pcb mounted, minimum
footprint
-
TYP. MAX. UNIT
-
50
1.2
-
K/W
K/W
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
V
GS(TO)
R
DS(ON)
Drain-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
GS
= 10 V; I
D
= 25 A
V
GS
= 5 V; I
D
= 25 A
V
GS
= 4.5 V; I
D
= 25 A
V
GS
= 5 V; I
D
= 25 A; T
j
= 175˚C
Gate source leakage current V
GS
=
±10
V; V
DS
= 0 V
Zero gate voltage drain
V
DS
= 25 V; V
GS
= 0 V;
current
T
j
= 175˚C
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal source inductance
Input capacitance
Output capacitance
Feedback capacitance
I
D
= 75 A; V
DD
= 44 V; V
GS
= 5 V
MIN.
55
42
1
0.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP. MAX. UNIT
-
-
1.5
-
-
7.4
8.6
9.1
-
0.02
0.05
-
55
13
28
19
114
250
216
3.5
7.5
3300
560
370
-
-
2
-
2.3
10.5
12
13
25
100
10
500
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
mΩ
mΩ
mΩ
mΩ
nA
µA
µA
nC
nC
nC
ns
ns
ns
ns
nH
nH
pF
pF
pF
I
GSS
I
DSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
s
C
iss
C
oss
C
rss
V
DD
= 30 V; R
D
= 1.2
Ω;
V
GS
= 10 V; R
G
= 10
Ω
Resistive load
Measured tab to centre of die
Measured from source lead to source
bond pad
V
GS
= 0 V; V
DS
= 20 V; f = 1 MHz
October 1999
2
Rev 1.200
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS™ transistor
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
I
S
I
SM
V
SD
t
rr
Q
rr
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
-
I
F
= 25 A; V
GS
= 0 V
I
F
= 25 A; -dI
F
/dt = 100 A/µs;
V
GS
= 0 V; V
R
= 25 V
-
-
-
PSMN010-55D
TYP. MAX. UNIT
-
-
0.95
70
0.16
75
240
1.2
-
-
A
A
V
ns
µC
October 1999
3
Rev 1.200
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS™ transistor
PSMN010-55D
Normalised Power Derating, PD (%)
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
175
10
Transient thermal impedance, Zth j-mb (K/W)
1
0.2
0.1
0.1
0.05
0.02
0.01
D = 0.5
P
D
tp
D = tp/T
single pulse
T
0.001
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
Pulse width, tp (s)
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Drain Current, ID (A)
VGS = 10V
5V
3V
2.8 V
Normalised Current Derating, ID (%)
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
175
50
45
40
35
30
25
20
15
10
5
0
0
Tj = 25 C
2.6 V
2.4 V
2.2 V
2V
0.2
0.4
0.6
0.8
1
1.2
1.4
Drain-Source Voltage, VDS (V)
1.6
1.8
2
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
Peak Pulsed Drain Current, IDM (A)
RDS(on) = VDS/ ID
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
)
1000
0.05
0.045
tp = 10 us
0.04
0.035
100 us
1 ms
0.03
0.025
Drain-Source On Resistance, RDS(on) (Ohms)
2.2 V
2.4 V
2.6 V
Tj = 25 C
2.8 V
100
10
0.02
0.015
3V
5V
VGS = 10V
D.C.
10 ms
100 ms
0.01
0.005
0
1000
0
5
10
15
20
25
30
Drain Current, ID (A)
35
1
1
10
100
Drain-Source Voltage, VDS (V)
40
45
50
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
)
October 1999
4
Rev 1.200
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS™ transistor
PSMN010-55D
Drain current, ID (A)
50
45
40
35
30
25
20
15
10
5
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
3
Gate-source voltage, VGS (V)
Tj = 25 C
VDS > ID X RDS(ON)
2.25
2
1.75
1.5
1.25
1
0.75
175 C
Threshold Voltage, VGS(TO) (V)
maximum
typical
minimum
0.5
0.25
0
-60
-40 -20
0
20
40
60
80
100 120 140 160 180
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
)
Transconductance, gfs (S)
VDS > ID X RDS(ON)
Tj = 25 C
175 C
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
1.0E-01
Drain current, ID (A)
1.0E-02
1.0E-03
minimum
typical
1.0E-04
maximum
1.0E-05
1.0E-06
0
5
10
15
20
25
30
35
Drain current, ID (A)
40
45
50
0
0.5
1
1.5
2
Gate-source voltage, VGS (V)
2.5
3
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
)
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Normalised On-state Resistance
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-60
-40
-20
0
20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
10000
Capacitances, Ciss, Coss, Crss (pF)
Ciss
1000
Coss
Crss
100
0.1
1
10
Drain-Source Voltage, VDS (V)
100
Fig.9. Normalised drain-source on-state resistance.
R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
)
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
October 1999
5
Rev 1.200
PCB设计
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