DISCRETE SEMICONDUCTORS
DATA SHEET
book, halfpage
M3D186
PDTA124ES
PNP resistor-equipped transistor
Product specification
Supersedes data of 1997 Jul 04
File under Discrete Semiconductors, SC04
1998 May 20
Philips Semiconductors
Product specification
PNP resistor-equipped transistor
FEATURES
•
Built-in bias resistors R1 and R2
(typ. 22 kΩ each)
•
Simplification of circuit design
•
Reduces number of components
and board space.
APPLICATIONS
•
Especially suitable for space
reduction in interface and driver
circuits
•
Inverter circuit configurations
without use of external resistors.
DESCRIPTION
PNP resistor-equipped transistor in a
TO-92; SOT54 plastic package.
NPN complement: PDTC124ES.
1
2
3
MGL136
MAM338
PDTA124ES
handbook, halfpage
2
R1
1
R2
3
1
2
3
Fig.1 Simplified outline (TO-92; SOT54) and symbol.
PINNING
PIN
1
2
3
DESCRIPTION
base/input
collector/output
emitter/ground (+)
Fig.2
Equivalent inverter
symbol.
QUICK REFERENCE DATA
SYMBOL
V
CEO
I
O
I
CM
P
tot
h
FE
R1
R2
------
-
R1
PARAMETER
collector-emitter voltage
output current (DC)
peak collector current
total power dissipation
DC current gain
input resistor
resistor ratio
T
amb
≤
25
°C
I
C
=
−5
mA; V
CE
=
−5
V
CONDITIONS
open base
MIN.
−
−
−
−
60
15.4
0.8
TYP.
−
−
−
−
−
22
1
MAX.
−50
−100
−100
500
−
28.6
1.2
kΩ
UNIT
V
mA
mA
mW
1998 May 20
2
Philips Semiconductors
Product specification
PNP resistor-equipped transistor
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V
CBO
V
CEO
V
EBO
V
I
PARAMETER
collector-base voltage
collector-emitter voltage
emitter-base voltage
input voltage
positive
negative
I
O
I
CM
P
tot
T
stg
T
j
T
amb
Note
1. Transistor mounted on an FR4 printed-circuit board.
THERMAL CHARACTERISTICS
SYMBOL
R
th j-a
Note
1. Transistor mounted on an FR4 printed-circuit board.
CHARACTERISTICS
T
amb
= 25
°C
unless otherwise specified.
SYMBOL
I
CBO
I
CEO
I
EBO
h
FE
V
CEsat
V
i(off)
V
i(on)
R1
R2
------
-
R1
C
c
PARAMETER
collector cut-off current
collector cut-off current
emitter cut-off current
DC current gain
input-off voltage
input-on voltage
input resistor
resistor ratio
collector capacitance
CONDITIONS
I
C
= 0; V
CB
=
−50
V
I
B
= 0; V
CE
=
−30
V
I
B
= 0; V
CE
=
−30
V; T
j
= 150
°C
I
C
= 0; V
EB
=
−5
V
I
C
=
−5
mA; V
CE
=
−5
V
I
C
=
−100 µA;
V
CE
=
−5
V
I
C
=
−5
mA; V
CE
=
−0.3
V
MIN.
−
−
−
−
60
−
−
−2.5
15.4
0.8
I
E
= i
e
= 0; V
CB
=
−10
V; f = 1 MHz
−
PARAMETER
thermal resistance from junction to ambient
CONDITIONS
note 1
VALUE
250
output current (DC)
peak collector current
total power dissipation
storage temperature
junction temperature
operating ambient temperature
T
amb
≤
25
°C;
note 1
−
−
−
−
−
−65
−
−65
CONDITIONS
open emitter
open base
open collector
−
−
−
MIN.
PDTA124ES
MAX.
−50
−50
−10
+10
−40
−100
−100
500
+150
150
+150
V
V
V
V
V
UNIT
mA
mA
mW
°C
°C
°C
UNIT
K/W
TYP.
−
−
−
−
−
−
−1.1
−1.7
22
1
−
MAX.
−100
−1
−50
−180
−
−150
−0.8
−
28.6
1.2
3
UNIT
nA
µA
µA
µA
mV
V
V
kΩ
collector-emitter saturation voltage I
C
=
−10
mA; I
B
=
−0.5
mA
pF
1998 May 20
3
Philips Semiconductors
Product specification
PNP resistor-equipped transistor
PDTA124ES
handbook, halfpage
10
3
MBK790
handbook, halfpage
(1)
(2)
(3)
−1
MBK789
hFE
VCEsat
(V)
10
2
−10
−1
(1)
(2)
(3)
10
1
−10
−1
−1
−10
IC (mA)
−10
2
−10
−2
−10
−1
−1
−10
IC (mA)
−10
2
V
CE
=
−5
V.
(1) T
amb
= 150
°C.
(2) T
amb
= 25
°C.
(3) T
amb
=
−40 °C.
I
C
/I
B
= 20.
(1) T
amb
= 100
°C.
(2) T
amb
= 25
°C.
(3) T
amb
=
−40 °C.
Fig.3
DC current gain as a function of collector
current; typical values.
Fig.4
Collector-emitter saturation voltage as a
function of collector current; typical values.
handbook, halfpage
−10
MBK792
−10
2
handbook, halfpage
Vi(on)
MBK791
Vi(off)
(V)
(V)
−10
(1)
(1)
(2)
(3)
−1
(2)
(3)
−1
−10
−1
−10
−2
−10
−1
−1
IC (mA)
−10
−10
−1
−10
−1
−1
−10
IC (mA)
−10
2
V
CE
=
−5
V.
(1) T
amb
=
−40 °C.
(2) T
amb
= 25
°C.
(3) T
amb
= 100
°C.
V
CE
=
−0.3
V.
(1) T
amb
=
−40 °C.
(2) T
amb
= 25
°C.
(3) T
amb
= 100
°C.
Fig.5
Input-off voltage as a function of collector
current; typical values.
Fig.6
Input-on voltage as a function of collector
current; typical values.
1998 May 20
4
Philips Semiconductors
Product specification
PNP resistor-equipped transistor
PACKAGE OUTLINE
Plastic single-ended leaded (through hole) package; 3 leads
PDTA124ES
SOT54
c
E
d
A
L
b
1
D
2
e1
e
3
b
1
L1
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
SOT54
REFERENCES
IEC
JEDEC
TO-92
EIAJ
SC-43
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
A
5.2
5.0
b
0.48
0.40
b1
0.66
0.56
c
0.45
0.40
D
4.8
4.4
d
1.7
1.4
E
4.2
3.6
e
2.54
e1
1.27
L
14.5
12.7
L1
(1)
2.5
1998 May 20
5
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