www.fairchildsemi.com
TDC1016
Video Speed D/A Converter
10-Bit, 20 Msps
Features
20 Msps conversion rate
8, 9, or 10-bit linearity
Voltage output, no amplifier required
Single supply operation (-5.2V, ECL compatible)
Dual supply operation (
±
5.0V, TTL compatible)
Internal 10-bit latched data register
Low glitch energy
Disabling controls, forcing full-scale, zero, and inverting
input data
• Binary or two’s complement input data formats
• Differential gain = 1.5%, differential phase = 1.0
°
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Description
The TDC1016 is a bipolar monolithic digital-to-analog
converter which can convert digital data into an analog volt-
age at rates up to 20 Msps (Megasamples Per Second). The
device includes an input data register and operates without
an external deglitcher or amplifier.
Operating the TDC1016 from a single -5.2V power supply
will bias the digital inputs for ECL levels, while operating
from a dual
±
5V power supply will bias the digital inputs for
TTL levels.
All versions of the TDC1016 are 10-bit digital-to-analog
converters, but are available with linearity specifications of
either 8, 9, or 10 bits. The TDC1016 is patented under U.S.
patent number 3283120 with other patents pending.
Applications
• Construction of video signals from digital data 3x or 4x
NTSC or PAL color subcarrier frequency
• CRT graphics displays, RGB, Raster, Vector
• Waveform synthesis
Block Diagram
10 TTL INPUTS
(20 ECL INPUTS)
CLK
(CLK)
NDIS
(NDIS)
NFL
NFH
N2C
VREF
COMP
A
65-1016-01
TTL/ECL
DIGITAL
INPUT
BUFFERS
DATA
LATCHED
10
10
CURRENT
SWITCHES
10
R–2R
RESISTOR
NETWORK
AOUT
CLK
VREF
Rev. 1.0.0
TDC1016
PRODUCT SPECIFICATION
Functional Description
General Information
TTL/ECL buffers are used for all digital inputs to the
TDC1016. Logic family compatibility depends upon the
connection of power supplies. When single power supply
(-5.2V) operation is employed, all data, clock, and disable
inputs are compatible with differential ECL logic levels. All
digital inputs become compatible with TTL levels when dual
power supply (
±
5.0V) operation is used.
The internal 10-bit register latches data on the rising edge of
the clock (CLK) pulse. Currents from the current sources are
switched accordingly and combined in the resistor network
to give an analog output voltage. The magnitude of the out-
put voltage is directly proportional to the magnitude of the
digital input word.
The NFL and NFH inputs can be used to simplify system
calibration by forcing the analog output voltage to either its
zero-scale or full-scale value. The TDC1016 can be operated
in binary, inverse binary, two’s complement or inverse two’s
complement input data formats.
The internal operational amplifier of the TDC1016 is fre-
quency stabilized by an external 1
m
F tantalum capacitor
connected between the COMP pin and V
EE
. A minimum of
1
m
F is adequate for most applications, but 10 microfarads or
more is recommended for optimum performance. The nega-
tive side of this capacitor should be connected to V
EE
.
Controls
The NDIS inputs are used to disable the TDC1016 by
forcing its output to the zero-scale value (current sources
off). The NDIS inputs are asynchronous, active without
regard to the CLK inputs. The other digital control inputs are
synchronous, latched on the rising edge of the CLK pulse.
The rising edge of the CLK pulse transfers data from the
input lines to the internal 10-bit register. In TTL mode, the
inverted inputs for CLK, DATA, and NDIS are inactive and
should be left open.
The Input Coding Table illustrates the function of the digital
control inputs. A two’s complement mode is created by acti-
vating N2C with a Logic 0 When NFH and NFL are both
activated with a Logic 0 the input data to the 10-bit register is
inverted.
Power
The TDC1016 can be operated from a single -5.2V power
supply or from a dual
±
5.0V power supply. For single power
supply operation, V
CC
is connected to D
GND
and all inputs
to the device become ECL compatible. When V
CC
is tied to
+5.0V, the inputs are TTL compatible.
The return path for the output from the 10 current sources is
A
GND
. The current return path for the digital section is
D
GND
. D
GND
and A
GND
should be returned to system
power supply ground by way of separate conductive paths to
prevent digital ground noise from disturbing the analog cir-
cuitry of the TDC1016. All A
GND
pins must be connected to
system analog ground.
Data Inputs
Data inputs are ECL compatible when single power supply
operation is employed. The J5 and C2 packages allow for
differential ECL inputs while the J7 and B7 packages have
only single-ended inputs. When differential ECL data is
used, any data input can be inverted simply by reversing the
connections to the true and inverted data input pins. All
inverted input pins should be left open if single-ended ECL
or TTL modes are used. All data inputs have an internal
40 K
W
pullup resistor to V
CC
.
Analog Output
The analog output voltage is negative with respect to A
GND
and varies proportionally with the magnitude of the input
data word. The output resistance at this point is 80
W
,
nominally.
Reference
The reference input is normally set to -1.0V with respect to
A
GND
. Adjusting this voltage is equivalent to adjusting sys-
tem gain The temperature stability of the TDC1016 analog
output (A
OUT
) depends primarily upon the temperature sta-
bility of the applied reference voltage
No Connects
There are several pins labeled no connect (NC) on the
TDC1016 J5 and C2 packages, which have no connections
to the chip. These pins should be left open.
2
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