Datasheet> 器件分类 > 存储> 存储> HYB39S256400CTL-7.5

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HYB39S256400CTL-7.5: 产品描述Synchronous DRAM, 64MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54; 产品类别存储存储; 文件大小456KB，共50页; 制造商Infineon(英飞凌); 官网地址http://www.infineon.com/

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HYB39S256400CTL-7.5概述

Synchronous DRAM, 64MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54

HYB39S256400CTL-7.5规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
厂商名称	Infineon(英飞凌)
零件包装代码	TSOP2
包装说明	TSOP2, TSOP54,.46,32
针数	54
Reach Compliance Code	compliant
ECCN代码	EAR99
访问模式	FOUR BANK PAGE BURST
最长访问时间	5.4 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	133 MHz
I/O 类型	COMMON
交错的突发长度	1,2,4,8
JESD-30 代码	R-PDSO-G54
JESD-609代码	e0
长度	22.22 mm
内存密度	268435456 bit
内存集成电路类型	SYNCHRONOUS DRAM
内存宽度	4
功能数量	1
端口数量	1
端子数量	54
字数	67108864 words
字数代码	64000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	64MX4
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	TSOP2
封装等效代码	TSOP54,.46,32
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	3.3 V
认证状态	Not Qualified
刷新周期	8192
座面最大高度	1.2 mm
自我刷新	YES
连续突发长度	1,2,4,8,FP
最大待机电流	0.002 A
最大压摆率	0.24 mA
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	3 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)
端子形式	GULL WING
端子节距	0.8 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	10.16 mm

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HYB39S256400/800/160CT(L)

256MBit Synchronous DRAM

256 MBit Synchronous DRAM

•

High Performance:

-7.5

fCK

tCK3

tAC3

tCK2

tAC2

133

7.5

5.4

-8

125

Units

MHz

•

Multiple Burst Read with Single Write

Operation

Automatic

Command

and

Controlled

Precharge

Data Mask for Read / Write control (x4, x8)

Data Mask for byte control (x16)

Auto Refresh (CBR) and Self Refresh

Power Down and Clock Suspend Mode

8192 refresh cycles / 64 ms (7,8

µs)

Random Column Address every CLK

( 1-N Rule)

Single 3.3V +/- 0.3V Power Supply

LVTTL Interface versions

Plastic Packages:

P-TSOPII-54 400mil width (x4, x8, x16)

-7.5 parts for PC133 3-3-3 operation

-8 parts for PC100 2-2-2 operation

•

Fully Synchronous to Positive Clock Edge

0 to 70

°C

operating temperature

Four Banks controlled by BA0 & BA1

Programmable CAS Latency: 2 & 3

Programmable Wrap Sequence: Sequential

or Interleave

Programmable Burst Length:

1, 2, 4, 8

Full page burst length for

sequential wrap around

The HYB39S256400/800/160CT(L) are four bank Synchronous DRAM’s organized as 4 banks x

16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices

achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that

prefetches multiple bits and then synchronizes the output data to a system clock. The chip is

fabricated with INFINEON’s advanced 0.17

µm

256MBit DRAM process technology.

The device is designed to comply with all industry standards set for synchronous DRAM products,

both electrically and mechanically. All of the control, address, data input and output circuits are

synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur

at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is

possible depending on burst length, CAS latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single

3.3V +/- 0.3V power supply and are available in TSOPII packages.

INFINEON Technologies

9.01

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