INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4066B
gates
Quadruple bilateral switches
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Quadruple bilateral switches
DESCRIPTION
The HEF4066B has four independent bilateral analogue
switches (transmission gates). Each switch has two
input/output terminals (Y/Z) and an active HIGH enable
input (E). When E is connected to V
DD
a low impedance
bidirectional path between Y and Z is established (ON
condition). When E is connected to V
SS
the switch is
HEF4066B
gates
disabled and a high impedance between Y and Z is
established (OFF condition).
The HEF4066B is pin compatible with the HEF4016B but
exhibits a much lower ON resistance. In addition the ON
resistance is relatively constant over the full input signal
range.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
PINNING
HEF4066BP(N): 14-lead DIL; plastic (SOT27-1)
HEF4066BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73))
HEF4066BT(D): 14-lead SO; plastic (SOT108-1)
( ): Package Designator North America
APPLICATION INFORMATION
An example of application for the HEF4066B is:
•
Analogue and digital switching
E
0
to E
3
Y
0
to Y
3
Z
0
to Z
3
enable inputs
input/output terminals
input/output terminals
Fig.3 Schematic diagram (one switch).
January 1995
2
Philips Semiconductors
Product specification
Quadruple bilateral switches
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Power dissipation per switch
For other RATINGS see Family Specifications
DC CHARACTERISTICS
T
amb
= 25
°C
V
DD
V
5
ON resistance
10
15
5
ON resistance
10
15
5
ON resistance
‘∆’ ON resistance
between any two
channels
OFF state leakage
current, any
channel OFF
E
n
input voltage
LOW
10
15
5
10
15
5
10
15
5
10
15
V
IL
I
OZ
∆R
ON
R
ON
R
ON
R
ON
SYMBOL
MIN.
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
2,25
4,50
6,75
TYP. MAX.
350
80
60
115
50
40
120
65
50
25
10
5
2500
Ω
245
Ω
175
Ω
340
Ω
160
Ω
115
Ω
365
Ω
200
Ω
155
Ω
−
−
−
−
−
Ω
Ω
Ω
nA
nA
1 V
2 V
2 V
E
n
at V
SS
P
max.
HEF4066B
gates
100
mW
CONDITIONS
E
n
at V
DD
V
is
= V
SS
to V
DD
see Fig.4
E
n
at V
DD
V
is
= V
SS
see Fig.4
E
n
at V
DD
V
is
= V
DD
see Fig.4
E
n
at V
DD
V
is
= V
SS
to V
DD
see Fig.4
200 nA
I
is
= 10
µA
see Fig.9
V
DD
V
SYMBOL
−40
T
amb
(°c)
+25
+85
MAX.
7,5
µA
15,0
µA
30,0
µA
1000 nA
CONDITIONS
MAX. MAX.
Quiescent device
current
Input leakage current at E
n
5
10
15
15
±
I
IN
I
DD
1,0
2,0
4,0
−
1,0
2,0
4,0
300
V
SS
= 0; all valid
input combinations;
V
I
= V
SS
or V
DD
E
n
at V
SS
or V
DD
January 1995
3
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4066B
gates
Fig.4 Test set-up for measuring R
ON
.
E
n
at V
DD
I
is
= 200
µA
V
SS
= 0 V
Fig.5 Typical R
ON
as a function of input voltage.
NOTE
To avoid drawing V
DD
current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the
bidirectional switch must not exceed 0,4 V. If the switch current flows into terminal Z, no V
DD
current will flow out of
terminals Y, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not
exceed V
DD
or V
SS
.
January 1995
4
Philips Semiconductors
Product specification
Quadruple bilateral switches
AC CHARACTERISTICS
(1)
,
(2)
V
SS
= 0 V; T
amb
= 25
°C;
input transition times
≤
20 ns
V
DD
V
Propagation delays
V
is
→
V
os
HIGH to LOW
5
10
15
5
LOW to HIGH
Output disable times
E
n
→
V
os
HIGH
5
10
15
5
LOW
Output enable times
E
n
→
V
os
HIGH
5
10
15
5
LOW
Distortion, sine-wave
response
Crosstalk between
any two channels
Crosstalk; enable
input to output
OFF-state
feed-through
ON-state frequency
response
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
t
PZL
t
PZH
40
20
15
45
20
15
0,25
0,04
0,04
−
1
−
−
50
−
−
1
−
−
90
−
80
40
30
90
40
30
ns
ns
ns
ns
ns
ns
%
%
%
MHz
MHz
MHz
mV
mV
mV
MHz
MHz
MHz
MHz
MHz
MHz
note 9
note 8
note 7
note 6
note 5
note 4
note 4
10
15
t
PLZ
t
PHZ
80
65
60
80
70
70
160
130
120
160
140
140
ns
ns
ns
ns
ns
ns
note 4
note 4
10
15
t
PLH
t
PHL
10
5
5
10
5
5
20
10
10
20
10
10
ns
ns
ns
ns
ns
ns
note 3
note 3
SYMBOL
TYP.
MAX.
HEF4066B
gates
January 1995
5
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