Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
PEDR27V6466F-01-08
1
Semiconductor
MR27V6466F
GENERAL DESCRIPTION
This version:
Jul. 2001
Previous version: Jun. 2001
Preliminary
4,194,304-Word x 16-Bit or 2,097,152-Word x 32-Bit Synchronous One Time PROM
The MR27V6466F is a 64 Mbit One Time Programmable Synchronous Read Only Memory whose configuration
can be electrically switched between 4,194,304 x 16 bit (word mode) and 2,097,152 x 32 bit (double word mode)
by the state of the
WORD
pin. The MR27V6466F supports high speed synchronous read operation using a single
3.3 V power supply.
FEATURES ON READ
•
•
•
•
•
3.3 V power supply
LVTTL compatible with multiplexed address
Dual electrically switchable configuration
4M x 16 (word mode) / 2M x 32 (double word mode)
All inputs are sampled at the rising edge of the system clock.
High speed read operation
100 MHz : CAS Latency = 5, 6
tRCD min: 2 clock cycles
66 MHz : CAS Latency = 5, 6
tRCD min: 2 clock cycles
50 MHz : CAS Latency = 4, 5, 6 tRCD min: 1 clock cycles
Burst length (4, 8)
Data scramble (sequential, interleave)
DQM for data out masking
No Precharge operation is required. No Refresh operation is required.
No power on sequence is required.
Mode register is automatically initialized to the default state after power on.
“Row Active” or “Mode Register Set” command is applicable as the first command just after power on.
Single Bank operation
Package: TSOP(2)86-P-400-0.50-K
(Product Name : MR27V6466FTA)
•
•
•
•
•
FEATURES ON PROGRAMMING
•
•
8.0 V programming power supply
Programming algorithm is compatible with conventional asynchronous OTP.
MR27V6466F can be programmed with conventional EPROM programmers.
Synchronous Burst read or Static Programming Operation is selected by the state of STO pin.
High STO level enables full static programming. (Program, Program Verify, Asynchronous Read)
Low STO level enables synchronous burst read.
Exclusive 86-pin socket adapters are available from OKI to support programming requirements.
The socket adapter is used on a 48-DIP socket on the programmer.
The socket adapter for 64M synchronous OTP is distinguished from the socket adapter for 32M SOTP.
The socket adapter is designed with the STO pin connected to V
CC
in order to program MR27V6466F as
conventional OTP.
EPROM programmer must have the algorithm for MR27V6466F on the exclusive socket adapter.
*Device damage can occur if improper algorithm is used.
Programming with address multiplexed input is also available.
High speed programming
25
µs
programming pulse per word allows high speed programming.
•
•
1/39
PEDR27V6466F-01-08
1
Semiconductor
MR27V6466F
BLOCK DIAGRAM
Row Address
Latch
Row Select
Row
Decoder
Column Address
Latch
A0
|
A12
Address Buffer
Memory Cell Array
2 M x 32 or 4 M x 16
Column Select
Column
Decoder
Sense Amplifier
& Program Bias
CS
RAS
CAS
MR
WORD
Mode
Register
Command
Controller
Burst sequence
Controller
Data Output
Latch
Data Input
Buffer
Data Output
Selector
CLK Buffer
Program Mode
Controller
Data Output / Input Buffer
& Data Output / Address Buffer
CKE
CLK
OE
CE
DQ0 to DQ15
STO DQ23 to DQ31
CAP0 to CAP8
AMPX
DQ16 to DQ22
2/39
PEDR27V6466F-01-08
1
Semiconductor
MR27V6466F
PIN CONFIGURATION
TOP VIEW
Programming in Static Operation (STO is high)
Synchronous Read (STO is V
SS
or open)
V
CC
DQ0
V
CC
Q
DC
DQ1
V
SS
Q
DC
DQ2
V
CC
Q
DC
DQ3
V
SS
Q
DC
DC
V
CC
DC
NC
CAS
RAS
DC
WORD
A12
A11
A10
A0
A1
A2
NC
V
CC
NC
DQ4
V
SS
Q
DC
DQ5
V
CC
Q
DC
DQ6
V
SS
Q
DC
DQ7
V
CC
Q
CAP8
V
CC
V
CC
DQ0
V
CC
Q
DQ16
DQ1
V
SS
Q
DQ17
DQ2
V
CC
Q
DQ18
DQ3
V
SS
Q
DQ19
MR
V
CC
DQM
NC
CAS
RAS
CS
WORD
A12
A11
A10
A0
A1
A2
NC
V
CC
NC
DQ4
V
SS
Q
DQ20
DQ5
V
CC
Q
DQ21
DQ6
V
SS
Q
DQ22
DQ7
V
CC
Q
DQ23
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
V
SS
DQ31
V
SS
Q
DQ15
DQ30
V
CC
Q
DQ14
DQ29
V
SS
Q
DQ13
DQ28
V
CC
Q
DQ12
NC
V
SS
DC
DC
DC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DC
V
SS
DC
DQ27
V
CC
Q
DQ11
DQ26
V
SS
Q
DQ10
DQ25
V
CC
Q
DQ9
DQ24
V
SS
Q
DQ8
V
SS
V
SS
CAP0
V
SS
Q
DQ15
CAP1
V
CC
Q
DQ14
CAP2
V
SS
Q
DQ13
CAP3
V
CC
Q
DQ12
NC
V
SS
V
PP
CE
OE
DC
DC
A9
A8
A7
A6
A5
A4
A3
AMPX
V
SS
STO
CAP4
V
CC
Q
DQ11
CAP5
V
SS
Q
DQ10
CAP6
V
CC
Q
DQ9
CAP7
V
SS
Q
DQ8
V
SS
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DC (Don’t Care) : Logical input level is ignored. However the pin is connected to the input
buffer of OTP.
3/39
PEDR27V6466F-01-08
1
Semiconductor
MR27V6466F
PIN FUNCTION FOR SYNCHRONOUS READ OPERATION
(STO pin is low level or open)
Pin Name
STO
CLK
CS
Function
Static Operation
System Clock
Chip Select
Description
Must be low for synchronous operation. Internal resistance
(around 10k ohms) pulls the input level down to V
SS
when this
pin is open. High level STO enables programming operation
compatible with standard OTPs.
All inputs are sampled at the rising edge.
Enables command sampling by the CLK signal with a low level
on the
CS
input.
Masks internal system clock to freeze the CLK operation of
subsequent CLK cycle. CKE must be enabled for command
sampling cycles. CLK is disabled for two types of operations.
1) Clock Suspend
2) Power Down
Row and column addresses are multiplexed on the same pins.
Row address: RA0 to RA12
Column address: CA0 to CA7 (x32) /CA0 to CA8 (x16)
LSB:CA0(Both x32 and x16)
RAS
CAS
MR
DQ0 to DQ31
DQM
Row Address Strobe
Column Address Strobe
Mode Register Set
Data Output
Data Output Masking
Functionality depends on the combination.
See the function table.
Data outputs are valid at the rising edge of CLK for read
cycles. Except for read cycles DQn is high-Z state.
Data outputs are masked after two cycles from when high level
DQM is applied.
The
WORD
pin defines the organization of each read
command to be x16 (word mode) or x32 (double word mode).
High = x32
Low = x16
When
WORD
is low (x16,word mode) ,DQ16 to DQ31 are
held on High-Z state.
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
DC
Power Supply
Ground
Data Output Power Supply
Data Output Ground
No Connection
Don't Care
Logical input level is ignored.
3.3 V Power supply to DQ0-DQ31
3.3 V Power supply
CKE
Clock Enable
A0 to A12
Address
WORD
x32/x16 Organization Selection
4/39
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