M89 FAMILY
In-System Programmable (ISP)
Multiple-Memory and Logic FLASH+PSD Systems for MCUs
DATA BRIEFING
s
s
Single Supply Voltage:
– 5 V±10% for M89xxFxY
– 3 V (+20/–10%) for M89xxFxW
1 or 2 Mbit of Primary Flash Memory (8 uniform
sectors, 16K x 8, or 32K x 8)
A second non-volatile memory:
– 256 Kbit (32K x 8) EEPROM (for M8913F1x)
or Flash memory (for M89x3F2x)
– 4 uniform sectors (8K x 8)
SRAM (16 Kbit, 2K x 8; or 64 Kbit, 8K x 8)
Over 2,000 Gates of PLD: DPLD and GPLD
27 Reconfigurable I/O ports
Enhanced JTAG Serial Port
Programmable power management
Stand-by current:
– 50
µA
for M89xxFxY
– 25
µA
for M89xxFxW
High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 10,000 Erase/Write Cycles of EEPROM
– 1,000 Erase/Write Cycles of PLD
PQFP52 (T)
s
s
s
s
s
s
s
s
PLCC52 (K)
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
PA0-PA7
PB0-PB7
PC0-PC7
PC2 = Voltage Stand-by
PD0-PD2
AD0-AD15
CNTL0-CNTL2
RESET
V
CC
V
SS
Port-D
Address/Data
Control
Reset
Supply Voltage
Ground
Port-A
Port-B
Port-C
8
PA0-PA7
3
CNTL0-
CNTL2
16
AD0-AD15
3
RESET
PD0-PD2
FLASH+PSD
8
PC0-PC7
8
PB0-PB7
VSS
AI02856
June 2000
Complete data available on
Data-on-Disc CD-ROM
or at
www.st.com
1/7
M89 FAMILY
Figure 2A. PLCC Connections
CNTL1
CNTL2
RESET
CNTL0
PB0
PB1
PB2
PB3
PB4
PB5
GND
PB6
PB7
Figure 2B. PQFP Connections
40 CNTLO
PD2
PD1
PD0
PC7
PC6
PC5
PC4
VCC
GND
PC3
PC2
PC1
PC0
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
46
45
44
43
42
41
40
39
38
37
36
35
34
27
28
29
31
32
30
33
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
VCC
AD7
AD6
AD5
AD4
GND 19
AD3 26
PA7 14
PA6 15
PA5 16
PA4 17
PA3 18
PA2 20
PA1 21
PA0 22
AD0 23
AD1 24
AD2 25
PD2 1
PD1 2
PD0 3
PC7 4
PC6 5
PC5 6
PC4 7
V
CC
8
GND 9
PC3 10
PC2 11
PC1 12
PC0 13
39 AD15
38 AD14
37 AD13
36 AD12
35 AD11
34 AD10
33 AD9
32 AD8
31 V
CC
30 AD7
29 AD6
28 AD5
27 AD4
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
AD1
AD2
GND
AD0
AD3
AI02857
41 RESET
43 CNTL1
42 CNTL2
46 GND
52 PB0
51 PB1
50 PB2
49 PB3
48 PB4
47 PB5
45 PB6
44 PB7
4
DESCRIPTION
The FLASH+PSD family of memory systems for
microcontrollers (MCUs) brings In-System-
Programmability (ISP) to Flash memory and
programmable logic. The result is a simple and
flexible solution for embedded designs.
FLASH+PSD devices combine many of the
peripheral functions found in MCU based
applications. FLASH+PSD provides a glueless
interface to most commonly-used ROMless
MCUs.
Table 2 summarizes all the devices in the M89
Family.
The FLASH+PSD device includes a JTAG Serial
Programming interface, to allow In-System
Programming (ISP) of the entire device. This
Table 2. Product Range
1
Part Number
M8913F1Y
M8913F2Y
M8934F2Y
M8913F1W
M8913F2W
M8934F2W
Primary Flash
Memory
1 Mbit
1 Mbit
2 Mbit
1 Mbit
1 Mbit
2 Mbit
Secondary NVM
256 Kbit EEPROM
256 Kbit Flash memory
256 Kbit Flash memory
256 Kbit EEPROM
256 Kbit Flash memory
256 Kbit Flash memory
SRAM
2
16 Kbit
16 Kbit
64 Kbit
16 Kbit
16 Kbit
64 Kbit
I/O Ports Voltage Range
27
27
27
27
27
27
2.7-3.6 V
150 ns
4.5-5.5 V
90 ns or
150 ns
Access Time
Note: 1. All products support: JTAG serial ISP, MCU parallel ISP, ISP Flash memory, ISP GPLD, Security features, Power Management
Unit (PMU), Automatic Power-down (APD)
2. SRAM may be backed up using an external battery.
7
5
3
2
52
51
50
49
48
47
6
1
AI02858
feature reduces development time, simplifies the
manufacturing flow, and dramatically lowers the
cost of field upgrades. Using ST’s special Fast-
JTAG programming, a design can be rapidly
programmed into the FLASH+PSD.
The innovative FLASH+PSD family solves key
problems faced by designers when managing
discrete Flash memory devices, such as:
– Complex address decoding
– In-System (first-time) Programming (ISP)
– Concurrent EEPROM or Flash memory
programming (IAP).
The JTAG Serial Interface block allows In-System
Programming (ISP). Embedded dual-bank
memories eliminates the need for an external Boot
2/7
ADDRESS/DATA/CONTROL BUS
PLD
INPUT
BUS
PAGE
REGISTER
EMBEDDED
ALGORITHM
8 SECTORS
POWER
MANGMT
UNIT
1 OR 2 MBIT MAIN FLASH
MEMORY
CNTL0,
CNTL1,
CNTL2
SECTOR
SELECTS
FLASH DECODE
PLD (DPLD)
57
SECTOR
SELECTS
SRAM SELECT
16 OR 64 KBIT BATTERY
BACKUP SRAM
256 KBIT SECONDARY
FLASH MEMORY
(BOOT OR DATA)
4 SECTORS
VSTDBY
(PC2)
Figure 3. FLASH+PSD Block Diagram
PROG.
MCU BUS
INTRF.
PROG.
PORT
PORT
A
PA0 – PA7
AD0 – AD15
CSIOP
RUNTIME CONTROL
AND I/O REGISTERS
ADIO
PORT
57
GPLD OUTPUT
FLASH ISP PLD
(GPLD)
PROG.
PORT
PORT
B
PB0 – PB7
GPLD OUTPUT
GPLD OUTPUT
PROG.
PORT
I/O PORT PLD INPUT
PORT
C
PC0 – PC7
GLOBAL
CONFIG. &
SECURITY
PROG.
PORT
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
JTAG
SERIAL
CHANNEL
PORT
D
PD0 – PD2
AI03765
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M89 FAMILY
3/7
M89 FAMILY
EPROM or Flash memory, or an external
programmer. To simplify Flash memory updates,
program execution is performed from a secondary
Flash memory (for the M89xxF2x) or EEPROM
(for the M8913F1x) while the primary Flash
memory is being updated. This solution avoids the
complicated hardware and software overhead
necessary to implement IAP.
ST makes available a software development tool,
PSDsoft Express, that generates ANSI-C
compliant code for use with your target MCU. This
code allows you to manipulate the non-volatile
memory (NVM) within the FLASH+PSD. Code
examples are also provided for:
– Flash memory IAP via the UART of the host
MCU
– Memory paging to execute code across several
FLASH+PSD memory pages
FLASH+PSD ARCHITECTURAL OVERVIEW
FLASH+PSD devices contain several major
functional blocks. Figure 3 shows the architecture
of the M89 FLASH+PSD device family. The
functions of each block are described briefly in the
following sections. Many of the blocks perform
multiple functions and are user configurable.
Memory
The 1 or 2 Mbit (128K x 8, or 256K x 8) Flash
memory is the primary memory of the
FLASH+PSD. It is divided into eight equally-sized
sectors that are individually selectable.
The 256 Kbit (32K x 8) secondary EEPROM or
Flash memory is divided into four equally-sized
sectors. Each sector is individually selectable.
The SRAM is intended for use as a scratch-pad
memory or as an extension to the MCU SRAM. If
an external battery is connected to Voltage Stand-
by (VSTBY, PC2), data is retained in the event of
power failure.
Each sector of memory can be located in a
different address space as defined by the user.
The access times for all memory types includes
the address latching and DPLD decoding time.
The M8913F1x has 64 bytes of OTP memory for
product identifiers, serial numbers, calibration
constants, etc..
Page Register
The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or
internal memory and I/O. The Page Register can
also be used to change the address mapping of
sectors of the Flash memories into different
memory spaces for IAP.
PLDs
The device contains two PLDs, the Decode PLD
(DPLD) and the General PLD (GPLD), each
optimized for a different function, as shown in
Table 3. The functional partitioning of the PLDs
reduces power consumption, optimizes cost/
performance, and eases design entry.
The Decode PLD (DPLD) is used to decode
addresses and to generate chip selects for the
FLASH+PSD internal memory and registers. The
DPLD has 14 combinatorial outputs, which are
used to select memory sectors and internal
registers. The General PLD (GPLD) can be used
to implement user-defined external chip select
signals and other combinatorial logic functions.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo bit in the PMMR0 register and other
bits in the PMMR2 registers. These registers are
set by the MCU at run-time. There is a slight
penalty to PLD propagation time when invoking
the power management features.
I/O Ports
The FLASH+PSD has 27 individually configurable
I/O pins distributed over the four ports (Port A, B,
C, and D). Each I/O pin can be individually
configured for different functions. Ports can be
configured as standard MCU I/O ports, PLD I/O, or
latched address outputs for MCUs using
multiplexed address/data buses. Ports A and B
can be configured to be open drain.
The JTAG pins can be enabled on Port C for In-
System Programming (ISP).
Port A can also be configured as a data port for a
non-multiplexed bus.
MCU Bus Interface
FLASH+PSD interfaces easily with most 8-bit
MCUs that have either multiplexed or non-
multiplexed address/data buses. The device is
configured to respond to the MCU’s control
signals, which are also used as inputs to the PLDs.
For examples, please see the full data sheet.
JTAG Port
In-System Programming (ISP) can be performed
through the JTAG signals on Port C. This serial
interface allows complete programming of the
entire FLASH+PSD device. A blank device can be
completely programmed for the first time after it is
soldered to the board. The JTAG signals (TMS,
TCK, TSTAT, TERR, TDI, TDO) can be
multiplexed with other functions on Port C. Table 4
indicates the JTAG pin assignments. Four-pin
JTAG is also fully supported.
In-System Programming (ISP)
Using the JTAG signals on Port C, the entire
FLASH+PSD device can be programmed or
4/7
M89 FAMILY
Table 3. PLD I/O
Name
Decode PLD (DPLD)
General PLD (GPLD)
Inpu ts
57
57
Outputs
14
19
Product
Terms
39
114
Table 4. JTAG SIgnals on Port C
Port C Pins
PC0
PC1
PC3
PC4
TMS
TCK
TSTAT
TERR
TDI
TDO
JTAG Signal
erased without the use of the MCU. The primary
Flash memory can also be programmed in-system
by the MCU executing the programming
algorithms out of the secondary memory, or
SRAM. The secondary memory can be
programmed the same way by executing out of the
primary Flash memory. The PLD or other
FLASH+PSD Configuration blocks can be
programmed through the JTAG port or a device
insertion programmer. Table 5 indicates which
programming methods can program different
functional blocks of the FLASH+PSD.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The FLASH+PSD also has some bits that are
configured at run-time by the MCU to reduce
power consumption of the GPLD. The Turbo bit in
the PMMR0 register can be reset to 0 and the
GPLD latches its outputs and goes to sleep until
the next transition on its inputs.
Additionally, bits in the PMMR2 register can be set
by the MCU to block signals from entering the
GPLD to reduce power consumption. Please see
the full data sheet for details.
SECURITY AND NVM SECTOR PROTECTION
A security bit in the Protection Register enables
the software project, coded in the FLASH+PSD, to
be locked up. This bit is only accessible by the
system designer from the JTAG serial port, or from
a parallel insertion programmer. It cannot be
PC5
PC6
accessed from the MCU. The only way a security
bit can be cleared is to erase the entire chip.
The contents of the sectors of the primary and
secondary NVM blocks can be protected using bits
in the Protection Registers. These bits are
accessible from the MCU in the application code,
or from a programmer during the set-up
procedure.
Table 5. Methods of Programming Different Functional Blocks of the FLASH+PSD
Functional Block
Primary Flash Memory
Secondary EEPROM or Flash memory
PLD Array (DPLD and GPLD)
FLASH+PSD Configuration
OTP Row
JTAG Programming
Yes
Yes
Yes
Yes
No
Device Programmer
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
IAP
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FPGA/CPLD
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