Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC8535EEC
Rev. 7, 07/2015
MPC8535E
MPC8535E PowerQUICC III
Integrated Processor
Hardware Specifications
• High-performance, 32-bit e500 core, scaling up to
1.25 GHz, that implements the Power Architecture®
technology
– 36-bit physical addressing
– Double-precision embedded floating point APU using
64-bit operands
– Embedded vector and scalar single-precision
floating-point APUs using 32- or 64-bit operands
– Memory management unit (MMU)
• Integrated L1/L2 cache
– L1 cache—32-Kbyte data and 32-Kbyte instruction
– L2 cache—512-Kbyte (8-way set associative)
• DDR2/DDR3 SDRAM memory controller with full ECC
support
– One 64-bit/32-bit data bus
– Up to 250-MHz clock (500-MHz data rate)
– Supporting up to 16 Gbytes of main memory
– Using ECC, detects and corrects all single-bit errors and
detects all double-bit errors and all errors within a nibble
– Invoke a level of system power management by
asserting MCKE SDRAM signal on-the-fly to put the
memory into a low-power sleep mode
– Both hardware and software options to support
battery-backed main memory
• Integrated security engine (SEC) optimized to process all
the algorithms associated with IPsec, IKE, SSL/TLS,
iSCSI, SRTP, IEEE Std 802.16e™, and 3GPP.
– XOR engine for parity checking in RAID storage
applications
• Enhanced Serial peripheral interfaces (eSPI)
– Support boot capability from eSPI
• Two enhanced three-speed Ethernet controllers (eTSECs)
with SGMII support
– Three-speed support (10/100/1000 Mbps)
– Two IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x,
IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and
IEEE Std 1588™-compatible controllers
MAPBGA–783
29 mm x 29 mm
•
•
•
•
•
•
•
•
•
•
•
•
– Support for various Ethernet physical interfaces: GMII,
TBI, RTBI, RGMII, MII, RGMII, RMII, and SGMII
– Support TCP/IP acceleration and QOS features
– MAC address recognition and RMON statistics support
– Support ARP parsing and generating wake-up events
based on the parsing results while in deep sleep mode
– Support accepting and storing packets while in deep
sleep mode
High-speed interfaces (multiplexed) supporting:
– Two PCI Express interfaces
– PCI Express 1.0a compatible
– One x4/x2/x1 PCI Express interface
– Two x2/x1 ports
– One SGMII interface
– One Serial ATA (SATA) controller supports SATA I and
SATA I data rates
PCI 2.2 compatible PCI controller
Two universal serial bus (USB) dual-role controllers
comply with USB specification revision 2.0
133-MHz, 32-bit, enhanced local bus (eLBC) with memory
controller
Enhanced secured digital host controller (eSDHC) used for
SD/MMC card interface
– Support boot capability from eSDHC
Integrated four-channel DMA controller
Dual I
2
C and dual universal asynchronous
receiver/transmitter (DUART) support
Programmable interrupt controller (PIC)
Power management, low standby power
– Support Doze, Nap, Sleep, Jog, and Deep Sleep mode
– PMC wake on: LAN activity, USB connection or remote
wakeup, GPIO, internal timer, or external interrupt event
System performance monitor
IEEE Std 1149.1™-compatible, JTAG boundary scan
783-pin FC-PBGA package, 29 mm
×
29 mm
Freescale reserves the right to change the detail specifications as may be required
to permit improvements in the design of its products.
© 2009-2011, 2014-2015 Freescale Semiconductor, Inc. All rights reserved.
Table of Contents
1
2
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .3
1.1 Pin Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .21
2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.4 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.5 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.6 DDR2 and DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . .31
2.7 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.8 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.9 Ethernet: Enhanced Three-Speed Ethernet (eTSEC),
MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.10 Ethernet Management Interface Electrical Characteristics
60
2.11 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.12 Enhanced Local Bus Controller (eLBC) . . . . . . . . . . . .65
2.13 Enhanced Secure Digital Host Controller (eSDHC) . . .74
2.14 Programmable Interrupt Controller (PIC) . . . . . . . . . . .76
2.15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
2.16 Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
2.17 I
2
C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
2.18 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
2.19 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
2.20 High-Speed Serial Interfaces . . . . . . . . . . . . . . . . . . . .90
2.21 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
3
2.23 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2.24 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 113
3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.2 Power Supply Design and Sequencing . . . . . . . . . . . 113
3.3 Pin States in Deep Sleep State . . . . . . . . . . . . . . . . . 114
3.4 Decoupling Recommendations . . . . . . . . . . . . . . . . . 114
3.5 SerDes
Block
Power
Supply
Decoupling
Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . 115
3.6 Connection Recommendations . . . . . . . . . . . . . . . . . 115
3.7 Pull-Up and Pull-Down Resistor Requirements . . . . . 115
3.8 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . 115
3.9 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . 116
3.10 JTAG Configuration Signals . . . . . . . . . . . . . . . . . . . 117
3.11 Guidelines for High-Speed Interface Termination . . . 119
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.1 Part Numbering Nomenclature . . . . . . . . . . . . . . . . . 121
4.2 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.3 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.1 Package Parameters for the FC-PBGA . . . . . . . . . . . 122
5.2 Mechanical Dimensions of the FC-PBGA . . . . . . . . . 124
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . 125
4
5
6
7
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
2
Freescale Semiconductor
Pin Assignments and Reset States
This figure shows the major functional units within the chip.
e500 Core
32-Kbyte
D-Cache
32-Kbyte
I-Cache
512-Kbyte
L2 Cache
Power
Management
MPC8535E
Performance
Monitor
Timers
Enhanced
Local Bus
SEC
OpenPIC
Coherency
Module
eSPI
DUART
2x I
2
C
64-bit
Async
DDR2/DDR3
Queue SDRAM Controller
with ECC
SD
MMC
USB
Host/
Device
ULPI
USB
Host/
Device
ULPI
Gigabit
Ethernet
w/ IEEE 1588
Gigabit
Ethernet
w/ IEEE 1588
SGMII
SerDes
PCI 32
SATA
PCI-e
DMA
PCI-e
4 Lane SerDes
Figure 1. Chip Block Diagram
1
Pin Assignments and Reset States
NOTE
The naming convention of TSEC1 and TSEC3 is used to allow the splitting voltage rails
for the eTSEC blocks and to ease the port of existing PowerQUICC III software
NOTE
The UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR
configuration. See
Table 1
for more details.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
3
Pin Assignments and Reset States
1.1
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MDQ
[44]
GND
MBA
[0]
MA
[10]
MAPAR_
OUT
GND
MCK
[3]
MCK
[0]
MA
[3]
MA
[6]
MA
[11]
MAPAR_
ERR
GND
MDQ
[26]
MDQ
[30]
MDQS
[3]
MDQ
[25]
MDQ
[29]
MDQ
[11]
MDQ
[15]
MDQS
[1]
MDQ
[9]
MDQ
[8]
MDQ
[12]
MDQ
[0]
Pin Map
B
GVDD
MDQ
[40]
MDQ
[45]
MWE
MBA
[1]
NC
MA
[0]
MCK
[3]
MCK
[0]
GND
See
Table 1
for the MPC8535E pinout, which is a subset of the MPC8536E.
C
MDQS
[5]
MDM
[5]
MDQ
[41]
MCS
[2]
MRAS
D
MDQ
[32]
MDQS
[5]
MCS
[0]
GVDD
E
MDQ
[46]
GVDD
F
MDQ
[47]
MDQ
[42]
MDQ
[33]
GND
G
MDQ
[34]
MDQ
[43]
GVDD
MDM
[4]
MDQ
[37]
MCS
[3]
GVDD
H
GND
MDQ
[35]
MDQ
[38]
J
MDQ
[56]
MDQ
[60]
MDQ
[52]
MDQ
[39]
MDQS
[4]
MCK
[2]
NC
K
MDQ
[57]
MDQ
[61]
GVDD
MDQ
[53]
MDQS
[4]
MCK
[2]
GND
L
GND
MDM
[7]
MDM
[6]
MDQ
[49]
MDQ
[48]
M
GVDD
MDQS
[7]
MDQS
[6]
MDQS
[6]
GND
N
MDQS
[7]
GND
MDQ
[50]
MDQ
[54]
GVDD
P
MDQ
[58]
MDM
[62]
MDQ
[51]
MDQ
[55]
GND
R
MDQ
[59]
MDQ
[63]
GVDD
Rvsd
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
USB1_
DIR
AVDD_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D USB1_ USB1_D USB1_D USB1_
RXD
SRDS2 RX_CLK RXD
TX_EN
RX_DV
STP
CLK
[7]
[0]
[2]
[5]
[3]
[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
MDQ
[36]
MODT
[0]
MODT
[2]
MCAS
GND
USB1_
AGND_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D USB1_D USB1_D USB1_
OVDD
PWR-
RXD
SRDS2 RXD
RX_DV GTX_CLK RXD
NXT
[6]
[1]
[3]
[4]
FAULT
[1]
[0]
[3]
SD2_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_ USB1_
PCTL0/ USB2_D USB2_D GND USB3_D USB3_D
PLL_
RXD
RXD
TXD
RXD RX_CLK RXD
[1]
[0]
[0]
[1]
GPIO[6]
[2]
[0]
[3]
[2]
[7]
TPA
USB1_
TSEC1_
TSEC3_
LVDD TSEC1_ PCTL1/ OVDD USB2_D USB2_D USB3_D USB3_D
TVDD
GND
GND
TXD
RX_ER
TX_CLK GPIO[7]
[3]
[2]
[2]
[3]
[1]
TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_
TXD GTX_CLK TX_EN
TXD
TXD
TXD
TX_ER
[1]
[2]
[4]
[6]
GND
USB2_ USB2_D USB2_D USB3_D USB3_
CLK
[4]
[4]
[5]
CLK
USB3_D USB3_D
[5]
[6]
USB3_ USB3_D
[7]
NXT
USB3_
DIR
USB2_
PCTL0/
GPIO[8]
USB3_
STP
Rsvd
GND
GVDD
MODT
[3]
MA
[13]
GND
MA
[7]
MA
[15]
MECC
[2]
GVDD
MCS
[1]
MODT
[1]
Rvsd
GND
GVDD
SD2_
SD2_
IMP_CAL REF_
_TX
CLK
SD2_
PLL_
TPD
Rsvd
SD2_
REF_
CLK
S2GND
GVDD
MA
[2]
GVDD
MA
[5]
MECC
[3]
NC
GND
MA
[4]
NC
MA
[12]
MECC
[7]
MDQS
[8]
MECC
[1]
GVDD
MDQ
[23]
GVDD
MA
[8]
MA
[14]
GVDD
SEE DETAIL
MCK
A
MCK
MA
[1]
GVDD
MCKE
[2]
GVDD
MECC
[0]
[5]
MCKE
[3]
MCKE
[0]
MCK
[1]
GVDD
MCK
[4]
GVDD
MDIC
[0]
LCS5/
DMA_
DREQ2
LA
[30]
LGPL3/
LFWP
LCS
[2]
LCS
[3]
LWE[3]/
LBS[3]
[5]
NC
GND
NC
MCKE
[1]
GND
Rsvd
S2VDD
GVDD
MCK
[1]
NC
X2GND
SD2_TX
[1]
GVDD
MA
[9]
MBA
[2]
MDQ
[27]
MDQ
[31]
MDQS
[3]
MDM
[3]
MDQ
[24]
MDQ
[28]
MDQ
[10]
MDQ
[14]
MDQS
[1]
MDM
[1]
MDQ
[13]
MDQ
[5]
MDQ
[1]
LDP
[2]
X2VDD
DMA_
TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ EC_GTX_ TSEC1_ USB2_D
SD2_RX
DACK[0]/ USB2_D OVDD
S2VDD TXD
RXD
RXD
TXD
RXD CLK125 COL
[0]
[6]
[7]
GPIO[10]
[0]
[5]
[4]
[0]
[4]
TSEC_
SD2_ TSEC3_
TSEC1_ USB2_ USB2_
USB2_
TVDD
LVDD
GND 1588_TRIG GND
GND
S2VDD SD2_RX IMP_CAL TXD
RXD
NXT
STP
DIR
[0]
_RX
[2]
_IN[1]
[6]
SDHC_
TSEC_ TSEC1_ TSEC1_ TSEC1_ USB2_
TSEC3_ TSEC3_ TSEC3_
SPI_
SPI_
SD2_RX
DAT[4]/SPI
NC
S2GND
PWR-
TXD
RXD
TXD
TXD
TXD 1588_TRIG TXD
MOSI
CLK
[1]
FAULT
_CS[0]
[7]
[5]
[5]
[3]
[5]
[6]
_IN[0]
SDHC_
USB2_
SPI_
TSEC3_ TSEC3_ TSEC3_ TSEC_ TSEC1_ TSEC1_
SD2_RX S2GND
PCTL1/
NC
GND DAT[6]/SPI
GND
1588_ RX_ER
TXD
COL
TX_ER
CRS
[1]
GPIO[9] MISO
_CS[2]
[4]
CLK
SDHC_ DMA_
SDHC_
DMA_ UART_
TSEC_ TSEC_
EC_
TSEC3_ TSEC3_ 1588_CLK
DAT[7]/SPI DREQ[0]/ DAT[5]/SPI OVDD DACK[1]/ SOUT
1588_TRIG
NC
NC
NC
MDC
CRS TX_CLK _OUT
GPIO[11]
_CS[3] GPIO[14] _CS[1]
_OUT[1]
[0]
TSEC_
TSEC_
TSEC_
DMA_ UART_
DMA_
DMA_
SD2_TX
MSRCID EC_ DDONE[0]/ DDONE[1]/ GND DREQ[1]/
OVDD
X2GND
X2VDD 1588_PULSE 1588_TRIG 1588_PULSE
CTS
MDIO GPIO[12] GPIO[13]
[4]
[0]
GPIO[15]
_OUT2 _OUT[0] _OUT1
[0]
S2GND
SEE DETAIL B
SDHC_ SDHC_
WP/GPIO CMD
[5]
SDHC_ SDHC_
CD/GPIO
DAT
[3]
[4]
SDHC_ SDHC_
DAT
DAT
[0]
[1]
SDHC_ SDHC_
DAT
CLK
[2]
IIC2_
SDA
HRESET_
REQ
HRESET
IRQ
[4]
SYSCLK
IIC2_
SCL
AVDD_
CORE
CKSTP_
OUT
GND
MECC
[6]
GVDD
GND
MDQS
[8]
GVDD
NC
MDM
[8]
MECC
[5]
GVDD
GND
MCK
[4]
GVDD
VDD_
CORE
GVDD
MDIC
[1]
LA
[28]
LA
[29]
LCS
[0]
LGPL5
TSEC3_ TSEC3_ MSRCID MSRCID UART_
X2GND SD2_TX X2VDD SD2_TX X2GND TXD
RXD
CTS
[0]
[2]
[1]
[0]
[7]
[7]
[1]
GND
VDD_
CORE
GND
VDD_
CORE
GND
LCS7/
DMA_
DDONE2
LA
[27]
VDD_
CORE
GND
VDD_
CORE
GND
VDD_
PLAT
GND
VDD_
PLAT
GND
VDD_
CORE
GND
VDD_
CORE
GND
VDD_
PLAT
GND
SD1_TX
[1]
SD1_TX
[1]
XGND
VDD_
CORE
GND
VDD_
CORE
GND
VDD_
PLAT
GND
VDD_
PLAT
XVDD
GND
VDD_
CORE
GND
VDD_
CORE
GND
VDD_
PLAT
GND
SD1_TX
[3]
SD1_TX
[3]
XVDD
VDD_ TSEC3_
MDVAL MSRCID
RXD
CORE
[1]
[6]
GND
VDD_
CORE
GND
VDD_
PLAT
GND
VDD_
PLAT
XVDD
VDD_
CORE
GND
VDD_
CORE
GND
VDD_
PLAT
GND
SENSE-
VDD_
CORE
SENSE-
VSS
VDD_
PLAT
GND
MSRCID
[3]
CLK_
OUT
PCI1_
REQ
[1]
SENSE-
VDD_
PLAT
PCI1_
GNT
[0]
GND
UART_
SOUT
[1]
TEST_
SEL
GND
UART_
RTS
[0]
GND
MECC
[4]
GND
MCP
UART_
GND
RTS
[1]
IRQ[10]/
IRQ[9]/
DMA_
OVDD DDRCLK DMA_
DACK[3] DREQ[3]
IRQ[11]/
PCI1_GNT
OVDD
UDE [4]/GPIO DMA_
DDONE[3]
[3]
PCI1_
AD
[31]
OVDD
PCI1_
AD
[27]
PCI1_
AD
[22]
PCI1_
AD
[21]
PCI1_
IRDY
PCI1_
PERR
PCI1_
AD
[28]
PCI1_
AD
[26]
IRQ_
OUT
OVDD
PCI1_
AD
[19]
PCI1_
AD
[16]
GND
PCI1_REQ
[4]/GPIO
[1]
PCI1_
IDSEL
PCI1_
AD
[23]
PCI1_
AD
[20]
PCI1_
AD
[17]
PCI1_
FRAME
GND
UART_
SIN
[0]
UART_
SIN
[1]
PCI1_
REQ
[2]
PCI1_
GNT
[2]
RTC
IRQ
[5]
IRQ
[1]
PCI1_
AD
[18]
IRQ
[3]
GND
MDQ
[19]
GVDD
MDQS
[2]
NC
GND
MDQ
[18]
MDQS
[2]
GVDD
MDQ
[16]
GND
LCS
[4]
LA
[31]
GND
LCS
[1]
LGPL2/
LOE/
LFRE
GND
LCS6/
DMA_
DACK2
GND
PCI1_REQ PCI1_GNT
[3]/GPIO [3]/GPIO
[0]
[2]
PCI1_
GNT
[1]
PCI1_
AD
[30]
OVDD
IRQ
[7]
XVDD
PCI1_
REQ
[0]
PCI1_
AD
[29]
PCI1_
AD
[25]
GND
L2_
TSTCLK
L1_
TSTCLK
GND
MDQ
[22]
MDQ
[21]
MDQ
[20]
BVDD
OVDD
PCI1_
AD
[24]
PCI1_
C_BE
[3]
GND
PCI1_
C_BE
[2]
GND
MDM
[2]
MDQ
[17]
GVDD
MDQ
[3]
MDQ
[6]
BVDD
CKSTP_ AVDD_
PLAT
IN
SRESET
AVDD_
DDR
BVDD
LGPL0/
LFCLE
BVDD
LWE0/
LBS0/
LFWE
TRIG_
GND OUT/READY TRIG_IN
/QUIESCE
SD1_TX
[4]
SD1_TX
[4]
XGND
XGND
SD1_TX
[6]
SD1_TX
[6]
XVDD
GND
GND
MDQ
[7]
GVDD
LAD
[27]
LAD
[24]
LDP
[3]
LAD
[22]
LAD
[21]
LAD
[20]
LGPL4/
LGTA/
LGPL1/
LUPWAIT/
XGND
LFALE
LPBSE/
LFRB
OVDD ASLEEP AVDD_
PCI1
PCI1_
TRDY
PCI1_
SERR
PCI1_
AD
[15]
OVDD
PCI1_
AD
[4]
PCI1_
AD
[2]
IIC1_
SCL
IRQ
[0]
TRST
IIC1_
SDA
PCI1_
AD
[11]
PCI1_
AD
[12]
PCI1_
C_BE
[0]
PCI1_
CLK
TMS
GVDD
MDQ
[2]
MDQS
[0]
GVDD
MDM
[0]
LAD
[25]
GND
GND
LAD
[31]
GND
LAD
[0]
LAD
[3]
LAD
[4]
LAD
[7]
LDP
[0]
LAD
[11]
LAD
[10]
LAD
[1]
LAD
[2]
BVDD
LAD
[5]
LAD
[6]
XVDD
SD1_TX
[0]
SD1_TX
[0]
XGND
XGND
SD1_TX
[2]
SD1_TX
[2]
SGND
SD1_RX
[1]
SD1_RX
[1]
XGND
XVDD
SD1_TX
[5]
SD1_TX
[5]
SGND
XGND
SEE DETAIL C
LAD
LWE[1]/
LAD
[29]
BVDD
LAD
[23]
LAD
[19]
LAD
[18]
GND
LAD
[17]
[30]
LAD
[28]
LAD
[26]
GND
LAD
[16]
LAD
[15]
LDP
[1]
LBS[1]
LWE[2]/
LBS[2]
LCLK
[0]
LCLK
[2]
BVDD
LAD
[14]
LAD
[13]
BVDD
LCLK
[1]
LBCTL
Rsvd
SEE
IRQ
DETAIL D
PCI1_
PCI1_
IRQ
SD1_TX
[7]
SD1_TX
[7]
SVDD
SD1_RX
[4]
[6]
[8]
PAR
PCI1_
AD
[13]
PCI1_
AD
[5]
C_BE
[1]
GND
PCI1_
AD
[7]
OVDD
XVDD
IRQ
[2]
SGND
PCI1_ PCI1_
DEVSEL STOP
OVDD
PCI1_
AD
[14]
PCI1_
AD
[9]
PCI1_
AD
[1]
GND
GND
MDQS
[0]
MDQ
[4]
XVDD
XGND
Rsvd
XVDD
XGND
GND
PCI1_
AD
[10]
PCI1_
AD
[8]
PCI1_
AD
[3]
PCI1_
AD
[6]
TCK
NC
SVDD
SVDD
SD1_RX
[3]
SD1_RX
[3]
SVDD
SGND
SVDD
SGND
NC
SVDD
SGND
SVDD
NC
SD1_
PLL_
TPA
AGND_
SRDS
SD1_
PLL_
TPD
SGND
SVDD
SD1_RX LSSD_
[6]
MODE
GND
LALE
GND
LAD
[9]
LAD
[8]
SD1_
IMP_CAL SGND
_RX
SVDD
SVDD
SD1_RX
[2]
SGND
SD1_
REF_
CLK
SD1_
REF_
CLK
SVDD
SD1_RX
SGND
[4]
SVDD
SD1_RX
[5]
SD1_RX
[5]
SD1_RX POWER_ PCI1_
AD
[6]
OK
[0]
SGND
SD1_RX
[7]
SD1_RX
[7]
GND
LSYNC_
IN
GND
LAD
[12]
SD1_RX SGND
[0]
SD1_RX
[0]
SVDD
NC
AVDD_
SRDS
SVDD POWER_ OVDD
EN
SD1_
SGND IMP_CAL
_TX
TDO
MVREF
GND
AVDD_ LSYNC_
LBIU
OUT
SGND
SD1_RX
SGND
[2]
SGND
SVDD
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
Figure 2. Chip Pin Map Bottom View
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
4
Freescale Semiconductor
Pin Assignments and Reset States
A
1
MDQ
[44]
B
GVDD
MDQ
[40]
MDQ
[45]
C
MDQS
[5]
MDM
[5]
MDQ
[41]
MCS
[2]
D
MDQ
[32]
MDQS
[5]
MCS
[0]
E
MDQ
[46]
F
MDQ
[47]
MDQ
[42]
MDQ
[33]
G
MDQ
[34]
MDQ
[43]
H
GND
J
MDQ
[56]
MDQ
[60]
MDQ
[52]
MDQ
[39]
MDQS
[4]
MCK
[2]
K
MDQ
[57]
MDQ
[61]
L
GND
M
GVDD
N
MDQS
[7]
P
MDQ
[58]
MDM
[62]
MDQ
[51]
MDQ
[55]
2
GVDD
MDQ
[35]
MDQ
[38]
MDM
[7]
MDM
[6]
MDQ
[49]
MDQ
[48]
SD2_
IMP_CAL
_TX
SD2_
PLL_
TPD
Rsvd
MDQS
[7]
MDQS
[6]
MDQS
[6]
GND
3
GND
GND
GVDD
MDM
[4]
MDQ
[37]
MCS
[3]
GVDD
MA
[1]
GVDD
MDQ
[53]
MDQS
[4]
MCK
[2]
MDQ
[50]
MDQ
[54]
4
MBA
[0]
MA
[10]
MAPAR_
OUT
MWE
GVDD
MDQ
[36]
MODT
[0]
MODT
[2]
GND
GND
5
MBA
[1]
MRAS
GND
GVDD
MODT
[3]
MA
[13]
GVDD
GND
SD2_
REF_
CLK
SD2_
REF_
CLK
S2GND
GVDD
GND
6
NC
GND
GVDD
MCS
[1]
MODT
[1]
MCK
[5]
MCKE
[3]
MCKE
[0]
MCK
[1]
S2GND
SD2_RX
[0]
SD2_RX
[0]
S2GND
7
GND
MA
[0]
MCK
[3]
MCK
[0]
GVDD
MA
[2]
NC
MCAS
NC
GND
S2VDD
SD2_RX
[1]
SD2_RX
[1]
NC
8
MCK
[3]
MCK
[0]
MA
[3]
MA
[6]
MA
[11]
MAPAR_
ERR
GND
GND
GVDD
MA
[8]
MA
[14]
GND
MCK
[5]
GND
9
GVDD
MA
[5]
MECC
[3]
MA
[4]
MA
[7]
MA
[15]
MECC
[2]
GVDD
NC
NC
Rsvd
S2VDD
S2GND
10
GND
NC
MCKE
[2]
GVDD
MCK
[1]
MCKE
[1]
NC
X2GND
NC
11
GVDD
MA
[12]
MECC
[7]
MDQS
[8]
MECC
[1]
GVDD
GVDD
GND
X2VDD
SD2_TX
[1]
SD2_TX
[1]
VDD_
CORE
X2GND
SD2_TX
[0]
SD2_TX
[0]
VDD_
CORE
12
MA
[9]
MBA
[2]
MDQ
[27]
GND
GND
NC
MECC
[0]
GVDD
GND
GVDD
VDD_
CORE
GVDD
X2GND
X2VDD
13
MECC
[6]
MDQS
[8]
MDM
[8]
MECC
[5]
GND
MCK
[4]
MCK
[4]
GND
GND
14
GVDD
GVDD
MECC
[4]
GVDD
GND
VDD_
CORE
GND
VDD_
CORE
GND
DETAIL A
Figure 3. Chip Pin Map Detail A
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
5
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