The LC74986NWF and LC74986NWV are video signal processing ICs that perform resolution conversion, interlaced
to progressive scan (IP) conversion, and image quality improvement without requiring the use of external field (frame)
memory. These ICs can display a wide variety of video signals and formats on a flat panel display. These ICs also
provide image quality improvement and adjustment functions to create the optimal image quality for the flat panel
display used. They also include an OSD function that displays characters with the sizes optimal for the size of panel
used. A flat panel TV monitor with the necessary video signal processing circuits can be formed easily by combining
one of these ICs with a video decoder, A/D converters, a microcontroller, and an LCD panel.
Features
• Multi-source support
— NTSC, PAL, and DTV (480i and 480p) inputs
— Progressive scan inputs up to XGA (The LC74986NWV supports up to SVGA.)
— Supports both RGB and YCbCr (4:4:4 24 bits, 4:2:2 16 bits or 8 bits) inputs (built-in YCbCr to RGB converter).
• Resolution conversion
— Independent horizontal and vertical expansion and reduction in the horizontal direction
— Interlaced to progressive scan conversion
• Image quality correction
— Sharpness, color, tint, white/black stretch, brightness, contrast, white balance, black balance
— Built-in lookup table based gamma correction circuit (Common characteristics for each 8-bit RGB value can be
programmed.)
• Panel interface
— Single RGB 24-bit or 18-bit, or dual RGB 48-bit or 36-bit signal output (built-in dither processing)
— Horizontal sync signal, vertical sync signal, data enable signal, and pixel clock outputs
• Other features
— No external frame memory required (The input and output have the same frame period.)
— Built-in OSD function (510 characters, 8 colors, built-in 8-character font RAM)
— I
2
C bus interface (The OSD function can also be controlled over a 3-wire bus.)
— Low-power design
IC Specifications
•
•
•
Supply voltage: I/O: 3.3V, core: 2.5V (LC74986NWF) or 1.8V (LC74986NWV) dual power supply system
Maximum operating frequency: 85MHz (LC74986NWF), 40MHz (LC74986NWV)
Package: 144-pin SQFP
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
40804TN (OT) No.7713-1/15
LC74986NWF, 74986NWV
Applications
• LCD TVs and LCD monitors
• Car TVs and car monitors
• PDP TVs
Specifications
Absolute Maximum Ratings
at Ta = 25°C, DV
SS
= 0V, AV
SS
= 0V. Values in parentheses apply to the
LC74986NWV. These are provisional specifications for the LC74986NWF.
Parameter
Maximum supply voltage
Input voltage
Output voltage
Allowable power dissipation
Storage temperature
Operating temperature
Symbol
V
DD
1
V
DD
2
V
I
V
O
Pd max
Tstg
Topr
Conditions
Ratings
–0.3 to +3.6
–0.3 to +4.6
–0.3 to V
DD
2+0.3
–0.3 to V
DD
2+0.3
TBD (0.6)
–55 to +125
–30 to +70
Unit
V
V
V
V
W
°C
°C
Allowable Operating Ranges
at Ta = –30 to +70°C. Values in parentheses apply to the LC74986NWV. These are
provisional specifications for the LC74986NWF.
Parameter
Supply voltage
Input voltage range
Symbol
V
DD
1
V
DD
2
V
IN
DV
DD
1
DV
DD
2, AV
DD
Conditions
Ratings
min
2.3 (1.7)
3.0
0
typ
2.5 (1.8)
3.3
max
2.7 (1.9)
3.6
3.6
Unit
V
V
V
DC Characteristics
at V
DD
1 = 2.5V (LC74986NWF) or 1.8V (LC74986NWV), V
DD
2 = 3.3V, Ta = –30 to +70°C.
These are provisional specifications for the LC74986NWF.
Parameter
Input high-level voltage
Input low-level voltage
Input high-level current
Input low-level current
Output high-level voltage
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Conditions
CMOS level inputs
CMOS level Schmitt inputs
CMOS level inputs
CMOS level Schmitt inputs
V
I
=V
DD
2
V
I
= V
DD
2, with a pull-down resistor used
V
I
=V
SS
B4 type, I
OH
=–2mA
B8 type, I
OH
=–4mA
B12 type, I
OH
=–6mA
B4 type, I
OL
=2mA
Output low-level voltage
Output leakage current
Pull-down resistance
Quiescent current
Quiescent current*
be guaranteed.
V
OL
I
OZ
R
DN
I
DD
1
I
DD
2
Outputs open, VI=V
SS
or V
DD
1
Outputs open, VI=V
SS
or V
DD
2
B8 type, I
OL
=4mA
B12 type, I
OL
=6mA
In high-impedance output mode
–10
126
300
10
–10
+10
–10
V
DD
2–0.4
V
DD
2–0.4
V
DD
2–0.4
0.4
0.4
0.4
+10
Ratings
min
0.7V
DD
2
0.75V
DD
2
0.2V
DD
2
0.15V
DD
2
+10
+100
+10
typ
max
Unit
V
V
V
V
µA
µA
µA
V
V
V
V
V
V
µA
kΩ
µA
µA
*:
Certain input pins have built-in pull-down resistors. Thus there are cases where, due to the circuit structure, the quiescent current characteristics cannot
No.7713-2/15
LC74986NWF, 74986NWV
Package Dimensions
unit : mm
3214
22.0
108
109
73
72
20.0
144
1
0.5
(1.25)
(1.4)
0.2
37
36
0.145
1.6max
0.1
SANYO : SQFP144
Input and Output Signals
• Input Signals Items shown in parentheses are alternate functions that can be selected by setting a register.
Signal type
Number of pins
8
8
Video signals
8
8
8
8
1
1
Sync signals
1
Symbol
VPA1
VPA2
VPA3
VPB1 (ROUT_2)
VPB2 (GOUT_2)
VPB3 (BOUT_2)
HSI
VSI
VPBH
VPBV
(AICS/PDOWN2)
Port A system horizontal sync signal • The input polarity is arbitrary. The IC discriminates
the polarity automatically.
Port A system vertical sync signal
Port B system horizontal sync signal
Port B system vertical sync signal
(Three-wire bus chip select, power
down)
Port A system horizontal data
enable, port A system composite
enable
• The input polarity is arbitrary. The IC discriminates
the polarity automatically.
• The input polarity is arbitrary. The IC discriminates
the polarity automatically.
• The pin can be selected by setting an internal register.
• The input polarity is arbitrary. It can be inverted
internally.
• DEVI must be held fixed at 1 when a composite
video signal is input.
• The input polarity is arbitrary. It can be inverted
internally.
• Only H/V composite signals are supported.
• The input polarity is arbitrary. It can be inverted
internally.
Input port B
(External video or dual output)
Input port A
• 24-bit RGB
• 24-bit YCbCr, 16-bit or 8-bit 4:2:2
Description
Notes
1
1
Data enable signals
1
22.0
DEHI
DEVI
VPBDEN
(VPBEN)
Port A system vertical data enable
Port B system composite data
enable
(External video enable)
1
0.5
20.0
Continued on next page.
No.7713-3/15
LC74986NWF, 74986NWV
Continued from preceding page.
Signal type
Number of pins
1
Pixel clock
1
1
Clock enable
Fixed oscillator
System reset
1
1
1
8
8
External video
8
1
Symbol
CLKI
DCLKI
VPBCK
CLKIEN
XTAL
RST
VPB1
VPB2
VPB3
VPBEN
(VPBDEN)
External video signal enable
(port B system composite data
enable)
External video signal
(input port B, dual output)
Description
Port A system clock
Display clock
Port B system clock
Port A system clock enable
Used for the control bus and
various detection functions
System reset
Notes
• Max85MHz(LC74986NWF),
Max40MHz(LC74986NWV)
• Max85MHz(LC74986NWF),
Max40MHz(LC74986NWV)
• Max85MHz(LC74986NWF),
Max40MHz(LC74986NWV)
• Positive logic
• Max85MHz(LC74986NWF),
Max40MHz(LC74986NWV)
• Inverted logic
• Inputs a video signal synchronized with the output
• Dither processing possible. Image quality
adjustments not possible.
• 6-bit input also possible
• Positive logic
• Output Signals
Signal type
Number of pins
8
8
Video signals
8
8
8
8
Sync signals
Data enable signals
1
1
1
1
1
Pixel clocks
1
1
1
Clamp levels
1
1
Divided output
signal for external
PLL circuit
1
Symbol
ROUT
GOUT
BOUT
ROUT_2 (VPB1)
GOUT_2 (VPB2)
BOUT_2 (VPB3)
HSO
VSO
DEHO
DEVO
CLKIO
DCLKO
CLPP
CLPVPA1
CLPVPA2
CLPVPA3
PLLHIO
R
G
B
Dual output
(input port B, external video
signal)
Horizontal sync signal
Vertical sync signal, composite signal
Horizontal data enable
Vertical data enable, composite enable
Outputs the input clock
Display clock
Used for A/D conversion
VP1 clamp level
VP2 clamp level
VP3 clamp level
For an external PLL circuit
Description
Notes
• Dithered 6-bit output also possible
• Dual output also possible. (Odd/even inversion possible)
• First data
• Dedicated dual system output. (Odd/even inversion
possible)
• Second data
• The sync signal, position, and polarity can be set.
• The polarity can be set.
• The polarity can be set.
• The polarity can be inverted.
• The polarity can be inverted. Divided-by-two output
possible in dual output mode.
• Output at the clamp position. The position can be
changed. The pulse width can be changed.
• Clamp level discrimination output
(Too large: low, too small: high, match: high
impedance)
Clamp pulse
No.7713-4/15
LC74986NWF, 74986NWV
• Control Signals
Signal type
Three-wire bus
signals
Number of pins
1
1
1
1
I
2
C bus signals
1
1
Symbol
AICS (VPBV)
AIDA
AICK
SDA
SCL
I
2
CSEL
Description
Three-wire bus chip select (port B
system vertical sync signal)
Data bus
Bus clock
Data bus
Bus clock
Slave switching
• Used for setting internal registers and for internal
status output.
• The slave address is 0111000 + (R/W)
• OSD control, gamma correction control
• Normally low. 0111000 + (R/W)
• Switches the IC to 0111001 + (R/W) when high.
• For OSD control (Normally, the I
2
C bus is used.)
Notes
• Other Signals
Signal type
Forcible mute
signal
Power down (low-
power mode) signal
Number of pins
1
2
1
Test signals
1
5
Symbol
MUTE
PDOWN1
PDOWN2 (VPBV)
SCANEN
SCANMOD
TEST
Muting
Low-power mode
(Port B system vertical sync signal)
Test
Test
Test
Description
Notes
• The output can be forcibly muted from this pin.
Inverted logic
• Low-power mode used when the IC is not operating.
This pin is normally held at the high level.
• Used for test settings. This pin must be held at the
low level during normal operation.
• Used for test settings. This pin must be held at the
low level during normal operation.
• Used for test settings. This pin must be held at the
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