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5962-8959823MTX

产品描述Standard SRAM, 128KX8, 100ns, CMOS, CDFP32,
产品类别存储    存储   
文件大小441KB,共91页
制造商White Microelectronics
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5962-8959823MTX概述

Standard SRAM, 128KX8, 100ns, CMOS, CDFP32,

5962-8959823MTX规格参数

参数名称属性值
厂商名称White Microelectronics
Reach Compliance Codeunknown
最长访问时间100 ns
JESD-30 代码R-CDFP-F32
长度20.825 mm
内存密度1048576 bit
内存集成电路类型STANDARD SRAM
内存宽度8
功能数量1
端子数量32
字数131072 words
字数代码128000
工作模式ASYNCHRONOUS
最高工作温度125 °C
最低工作温度-55 °C
组织128KX8
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码DFP
封装形状RECTANGULAR
封装形式FLATPACK
并行/串行PARALLEL
认证状态Not Qualified
座面最大高度3.175 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子形式FLAT
端子节距1.27 mm
端子位置DUAL
宽度10.415 mm

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REVISIONS
LTR
H
DESCRIPTION
Add device type 41. Make corrections to case outline N, dimension b.
Add vendor CAGE 65786 as source of supply for device type 41.
Update boilerplate. Editorial changes throughout.
Add device types 42, 43, 44, 45, and 46. Editorial changes to pages
1, 3, 7-15. Update boilerplate. ksr
Added provisions to accommodate radiation-hardened devices.
Added device type 47 to drawing. glg
Corrected case outline 8 Figure 1 to show correct numbering of
terminals. Corrected Figure 2 Terminal connections. Corrected the
case outline Y Figure 1 to show the proper distance of E and E1.
Added note to Case outline Y Figure 1, to allow for bottom brazed
package as an alternative style to the side brazed package . Update
boilerplate. Editorial changes throughout. ksr
Changed the minimum value for the Q dimension on package T from
0.026 to 0.020 and removed footnote 12. Editorial changes
throughout.. ksr
Added device type 48 to drawing. ksr
Corrected typo on Figure 4 (Read Cycle). ksr
Vendor requested change in capacitance in Table I for devices 39 and
40 from 5 pF to 8 pF. ksr
DATE (YR-MO-DA)
97-03-26
APPROVED
Raymond Monnin
J
K
L
98-03-03
00-03-01
00-12-08
Raymond Monnin
Raymond Monnin
Raymond Monnin
M
02-12-19
Raymond Monnin
N
P
R
03-08-12
05-08-16
06-02-13
Raymond Monnin
Raymond Monnin
Raymond Monnin
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
R
35
R
15
R
36
R
16
R
37
R
17
R
38
R
18
REV
R
39
R
19
R
40
R
20
R
41
R
21
R
1
R
42
R
22
R
2
R
43
R
23
R
3
R
44
R
24
R
4
R
45
R
25
R
5
R
46
R
26
R
6
R
47
R
27
R
7
R
48
R
28
R
8
R
49
R
29
R
9
R
50
R
30
R
10
R
51
R
31
R
11
R
52
R
32
R
12
R
33
R
13
R
34
R
14
SHEET
PREPARED BY
Kenneth S. Rice
CHECKED BY
Raymond Monnin
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
APPROVED BY
Michael A. Frye
DRAWING APPROVAL DATE
89-04-21
REVISION LEVEL
R
MICROCIRCUIT, MEMORY, DIGITAL,
CMOS, 128K X 8 STATIC RANDOM
ACCESS MEMORY (SRAM) LOW POWER,
MONOLITHIC SILICON
SIZE
A
SHEET
CAGE CODE
67268
1 OF
52
5962-89598
5962-E261-06
DSCC FORM 2233
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