INTEGRATED CIRCUITS
SCC2692
Dual asynchronous receiver/transmitter
(DUART)
Product specification
Supersedes data of 1998 Feb 19
IC19 Data Handbook
1998 Sep 04
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
DESCRIPTION
The Philips Semiconductors SCC2692 Dual Universal
Asynchronous Receiver/Transmitter (DUART) which is compatible
with the SCN2681. It is a single-chip CMOS-LSI communications
device that provides two full-duplex asynchronous
receiver/transmitter channels in a single package. It interfaces
directly with microprocessors and may be used in a polled or
interrupt driven system.
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16X clock derived from a programmable counter/timer,
or an external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
Each receiver is quadruply buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable a
remote DUART transmitter when the receiver buffer is full.
Also provided on the SCC2692 are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
–
Non-standard user-defined rate derived from programmable
counter/timer
–
External 1X or 16X clock
•
Parity, framing, and overrun error detection
•
False start bit detection
•
Line break detection and generation
•
Programmable channel mode
–
Normal (full-duplex)
–
Automatic echo
–
Local loopback
–
Remote loopback
–
Multidrop mode (also called ‘wake-up’ or ‘9-bit’)
•
Multi-function 7-bit input port
–
Can serve as clock or control inputs
–
Change of state detection on four inputs
–
Inputs have typically >100k pull-up resistors
•
Multi-function 8-bit output port
–
Individual bit set/reset capability
–
Outputs can be programmed to be status/interrupt signals
•
Versatile interrupt system
–
Single interrupt output with eight maskable interrupting
conditions
–
Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
FEATURES
•
Dual full-duplex asynchronous receiver/transmitters
•
Quadruple buffered receiver data register
•
Programmable data format
–
5 to 8 data bits plus parity
–
Odd, even, no parity or force parity
–
1, 1.5 or 2 stop bits programmable in 1/16-bit increments
•
16-bit programmable Counter/Timer
•
Programmable baud rate for each receiver and transmitter
selectable from:
–
22 fixed rates: 50 to 115.2k baud
–
Non-standard rates to 115.2Kb
•
Maximum data transfer rates: 1X – 1MB/sec, 16X – 125kB/sec
•
Automatic wake-up mode for multidrop applications
•
Start-end break interrupt/status
•
Detects break which originates in the middle of a character
•
On-chip crystal oscillator
•
Power down mode
•
Receiver timeout mode
•
Commercial and industrial temperature range versions
•
TTL compatible
•
Single +5V power supply
ORDERING INFORMATION
COMMERCIAL
DESCRIPTION
40-Pin Plastic Dual In-Line Package (DIP)
1
28-Pin Plastic Dual In-Line Package (DIP)
1
44-Pin Plastic Leaded Chip Carrier (PLCC) Package
44–Pin Plastic Quad Flat Pack (PQFP)
NOTE:
1. For availability, please contact factory.
V
CC
= +5V +10%,
T
A
= 0 to +70°C
SCC2692AC1N40
SCC2692AC1N28
SCC2692AC1A44
SCC2692AC1B44
INDUSTRIAL
V
CC
= +5V +10%,
T
A
= -40 to +85°C
SCC2692AE1N40
SCC2692AE1N28
SCC2692AE1A44
SCC2692AE1B44
DWG #
SOT129-1
SOT117-1
SOT187-2
SOT307–2
1998 Sep 04
2
853–0895 19971
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
A0
IP3
A1
IP1
A2
A3
IP0
WRN
1
2
3
4
5
6
7
8
40 V
CC
39 IP4
38 IP5
37 IP6
36 IP2
35 CEN
34 RESET
33 X2
32 X1/CLK
31 RxDA
DIP
30 TxDA
29 OP0
28 OP2
27 OP4
26 OP6
25 D0
24 D2
23 D4
22 D6
21 INTRN
A0
A1
A2
A3
WRN
RDN
RxDB
TxDB
OP1
D1
D3
1
2
3
4
5
6
7
DIP
8
9
10
11
INDEX
CORNER
7
28 V
CC
27 IP2
26 CEN
25 RESET
24 X2
23 X1/CLK
22 RxDA
21 TxDA
20 OP0
19 D0
18 D2
17 D4
16 D6
15 INTRN
17
6
1
40
39
1
44
34
33
PLCC
PQFP
29
18
TOP VIEW
28
11
12
TOP VIEW
22
23
RDN 9
RxDB 10
TxDB 11
OP1 12
OP3
13
PIN/FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
A0
IP3
A1
IP1
A2
A3
IP0
WRN
RDN
RXDB
NC
TXDB
OP1
OP3
OP5
OP7
D1
D3
D5
D7
GND
PIN/FUNCTION
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NC
INTRN
D6
D4
D2
D0
OP6
OP4
OP2
OP0
TXDA
NC
RXDA
X1/CLK
X2
RESET
CEN
IP2
IP6
IP5
IP4
V
CC
PIN/FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A3
IP0
WRN
RDN
RxDB
TxDB
OP1
OP3
OP5
OP7
N/C
D1
D3
D5
D7
GND
GND
INTRN
D6
D4
D2
D0
PIN/FUNCTION
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
N/C
OP6
OP4
OP2
OP0
TxDA
RxDA
X1/CLK
X2
RESET
CEN
IP2
IP6
IP5
IP4
V
CC
V
CC
A0
IP3
A1
IP1
A2
OP5 14
OP7 15
D1 16
D3 17
D5 18
D7 19
GND 20
D5 12
D7
13
GND 14
SD00131
Figure 1. Pin Configurations
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
T
A
T
STG
V
CC
V
S
PARAMETER
Operating ambient temperature range
2
Storage temperature range
Voltage from V
CC
to GND
3
Voltage from any pin to GND
3
Package power dissipation
P
D
Package power dissipation
Package power dissipation
Package power dissipation
Derating factor above 25°C
Derating factor above 25°C
Derating factor above 25°C
Derating factor above 25°C
DIP28
DIP40
PLCC44
PQFP44
DIP28
DIP40
PLCC44
PQFP44
RATING
Note 4
-65 to +150
-0.5 to +7.0
-0.5 to V
CC
+0.5
1.22
2.97
2.66
2.08
19
24
21
17
UNIT
°C
°C
V
V
W
W
W
W
mW/°C
mW/°C
mW/°C
mW/°C
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range.
1998 Sep 04
3
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
BLOCK DIAGRAM
8
D0–D7
BUS BUFFER
CHANNEL A
TRANSMIT
HOLDING REG
TRANSMIT
SHIFT REGISTER
TxDA
RDN
WRN
CEN
A0–A3
RESET
4
OPERATION CONTROL
ADDRESS
DECODE
R/W CONTROL
RECEIVE
HOLDING REG (3)
RxDA
RECEIVE
SHIFT REGISTER
MRA1, 2
CRA
SRA
INTERRUPT CONTROL
INTRN
IMR
ISR
CHANNEL B
(AS ABOVE)
TxDB
RxDB
INTERNAL DATABUS
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
IPCR
ACR
CONTROL
TIMING
BAUD RATE
GENERATOR
TIMING
7
IP0-IP6
CLOCK
SELECTORS
COUNTER/
TIMER
OUTPUT PORT
FUNCTION
SELECT LOGIC
8
X1/CLK
XTAL OSC
X2
CSRA
CSRB
ACR
U
CTLR
CTLR
OP0-OP7
OPCR
OPR
V
CC
GND
SD00132
Figure 2. Block Diagram
1998 Sep 04
4
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCC2692
PIN DESCRIPTION
SYMBOL
D0-D7
CEN
APPLICABLE
40,44
28
X
X
X
X
TYPE
I/O
I
NAME AND FUNCTION
Data Bus:
Bidirectional 3-State data bus used to transfer commands, data and status between the
DUART and the CPU. D0 is the least significant bit.
Chip Enable:
Active-Low input signal. When Low, data transfers between the CPU and the DUART
are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When High, places the
D0-D7 lines in the 3-State condition.
Write Strobe:
When Low and CEN is also Low, the contents of the data bus are loaded into the
addressed register. The transfer occurs on the rising edge of the signal.
Read Strobe:
When Low and CEN is also Low, causes the contents of the addressed register to be
presented on the data bus. The read cycle begins on the falling edge of RDN.
Address Inputs:
Select the DUART internal registers and ports for read/write operations.
Reset:
A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0-OP7 in
the High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA
and TxDB outputs in the mark (High) state. Resets Test modes, MR pointer set to MR1.
Interrupt Request:
Active-Low, open-drain, output which signals the CPU that one or more of the
eight maskable interrupting conditions are true.
Crystal 1:
Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing.
Crystal 2:
Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not
connected although it is permissible to ground it.
Channel A Receiver Serial Data Input:
The least significant bit is received first. “Mark” is High,
“space” is Low.
Channel B Receiver Serial Data Input:
The least significant bit is received first. “Mark” is High,
“space” is Low.
Channel A Transmitter Serial Data Output:
The least significant bit is transmitted first. This output is
held in the “mark” condition when the transmitter is disabled, idle or when operating in local loopback
mode. “Mark” is High, “space” is Low.
Channel B Transmitter Serial Data Output:
The least significant bit is transmitted first. This output
is held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local
loopback mode. ‘Mark’ is High, ‘space’ is Low.
Output 0:
General purpose output or Channel A request to send (RTSAN, active-Low). Can be
deactivated automatically on receive or transmit.
Output 1:
General purpose output or Channel B request to send (RTSBN, active-Low). Can be
deactivated automatically on receive or transmit.
Output 2:
General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A
receiver 1X clock output.
Output 3:
General purpose output or open-drain, active-Low counter/timer output or Channel B
transmitter 1X clock output, or Channel B receiver 1X clock output.
Output 4:
General purpose output or Channel A open-drain, active-Low, RxRDYAN/FFULLAN output.
Output 5:
General purpose output or Channel B open-drain, active-Low, RxRDYBN/FFULLBN output.
Output 6:
General purpose output or Channel A open-drain, active-Low, TxRDYAN output.
Output 7:
General purpose output, or Channel B open-drain, active-Low, TxRDYBN output.
Input 0:
General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an
internal V
CC
pull-up device supplying 1 to 4
mA
of current.
Input 1:
General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an
internal V
CC
pull-up device supplying 1 to 4
mA
of current.
Input 2:
General purpose input or counter/timer external clock input. Pin has an internal V
CC
pull-up
device supplying 1 to 4
mA
of current.
Input 3:
General purpose input or Channel A transmitter external clock input (TxCA). When the
external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock. Pin has an internal V
CC
pull-up device supplying 1 to 4
mA
of current.
Input 4:
General purpose input or Channel A receiver external clock input (RxCA). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V
CC
pull-up device supplying 1 to 4
mA
of current.
Input 5:
General purpose input or Channel B transmitter external clock input (TxCB). When the
external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock. Pin has an internal V
CC
pull-up device supplying 1 to 4
mA
of current.
Input 6:
General purpose input or Channel B receiver external clock input (RxCB). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V
CC
pull-up device supplying 1 to 4
mA
of current.
Power Supply:
+5V supply input.
Ground
5
WRN
RDN
A0-A3
RESET
X
X
X
X
X
X
X
X
I
I
I
I
INTRN
X1/CLK
X2
RxDA
RxDB
TxDA
X
X
X
X
X
X
X
X
X
X
X
X
O
I
I
I
I
O
TxDB
X
X
O
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
IP0
IP1
IP2
IP3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
O
O
O
O
O
O
O
O
I
I
X
I
I
IP4
X
I
IP5
X
I
IP6
X
I
V
CC
GND
1998 Sep 04
X
X
X
X
I
I
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
