UNISONIC TECHNOLOGIES CO., LTD
MJE13003
NPN SILICON POWER
TRANSISTORS
DESCRIPTION
These devices are designed for high–voltage, high–speed
power switching inductive circuits where fall time is critical. They
are particularly suited for 115 and 220V SWITCHMODE .
1
NPN EPITAXIAL SILICON TRANSISTOR
FEATURES
* Reverse Biased SOA with Inductive Load @ Tc=100℃
* Inductive Switching Matrix 0.5 ~ 1.5 Amp, 25 and 100℃
Typical tc = 290ns @ 1A, 100℃.
* 700V Blocking Capability
TO-252
APPLICATIONS
* Switching Regulator’s, Inverters
* Motor Controls
* Solenoid/Relay drivers
* Deflection circuits
*Pb-free plating product number: MJE13003L
ORDERING INFORMATION
Normal
Order Number
Lead Free Plating
Package
TO-252
TO-252
MJE13003-x-TN3-F-R
MJE13003L-x-TN3-F-R
MJE13003-x-TN3-F-T
MJE13003L-x-TN3-F-T
Note: x: Rank, refer to Classification of h
FE1
.
Pin Assignment
1
2
3
B
C
E
B
C
E
Packing
Tape Reel
Tube
MJE13003L-x-TN3-F-R
(1)Packing Type
(2)Pin Assignment
(3)Package Type
(4)Rank
(5)Lead Plating
(1) R: Tape Reel, T: Tube
(2) refer to Pin Assignment
(3) TN3: TO-252
(4) x: refer to Classification of h
FE1
(5) L: Lead Free Plating, Blank: Pb/Sn
www.unisonic.com.tw
Copyright © 2005 Unisonic Technologies Co., Ltd
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QW-R209-022,A
MJE13003
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Collector-Emitter Voltage
Collector-Emitter Voltage
Emitter Base Voltage
NPN EPITAXIAL SILICON TRANSISTOR
SYMBOL
RATINGS
UNIT
V
CEO(SUS)
400
V
V
CEO
700
V
V
EBO
9
V
Continuous
I
C
1.5
Collector Current
A
Peak (1)
I
CM
3
Continuous
I
B
0.75
Base Current
A
Peak (1)
I
BM
1.5
Continuous
I
E
2.25
Emitter Current
A
Peak (1)
I
EM
4.5
Total Power Dissipation (T
C
=25℃)
P
D
25
W
℃
Junction Temperature
T
J
150
℃
Storage Temperature
T
STG
-40 ~ +150
Note Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
ELECTRICAL CHARACTERISTICS
(T
C
=25°C, unless otherwise specified.)
PARAMETER
OFF CHARACTERISTICS (Note)
Collector-Emitter Sustaining Voltage
Collector Cutoff Current
Emitter Cutoff Current
SECOND BREAKDOWN
Second Breakdown Collector Current
with bass forward biased
Clamped Inductive SOA with base
reverse biased
ON CHARACTERISTICS (Note)
DC Current Gain
SYMBOL
TEST CONDITIONS
MIN
400
T
C
=25°C
T
C
=100℃
1
5
1
TYP
MAX
UNIT
V
mA
mA
V
CEO(SUS)
I
C
=10 mA , I
B
=0
V
CEO
=Rated Value,
I
CEO
V
BE(OFF)
=1.5 V
I
EBO
V
EB
=9 V, I
C
=0
Is/b
RBSOA
See Figure 5
See Figure 6
h
FE1
h
FE2
V
CE(SAT
)
Collector-Emitter Saturation Voltage
Base-Emitter Saturation Voltage
DYNAMIC CHARACTERISTICS
Current-Gain-Bandwidth Product
Output Capacitance
SWITCHING CHARACTERISTICS
Resistive Load (Table 1)
Delay Time
Rise Time
Storage Time
Fall Time
V
BE(SAT)
I
C
=0.5A, V
CE
=2V
I
C
=1A, V
CE
=2V
I
C
=0.5A, I
B
=0.1A
I
C
=1A, I
B
=0.25A
I
C
=1.5A, I
B
=0.5A
I
C
=1A, I
B
=0.25A, T
C
=100℃
I
C
=0.5A, I
B
=0.1A
I
C
=1A, I
B
=0.25A
I
C
=1A, I
B
=0.25A, T
C
=100℃
I
C
=100mA, V
CE
=10V, f=1MHz
V
CB
=10V, I
E
=0, f=0.1MHz
8
5
40
25
0.5
1
3
1
1
1.2
1.1
10
21
V
V
f
T
Cob
4
MHz
pF
t
D
t
R
t
S
t
FALL
V
CC
=125V, I
C
=1A, I
B1
=I
B2
=0.2A,
t
P
=25μs, Duty Cycle≤1%
0.05
0.5
2
0.4
0.1
1
4
0.7
μs
μs
μs
μs
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ELECTRICAL CHARACTERISTICS(Cont.)
Inductive Load, Clamped (Table 1)
Storage Time
Crossover Time
Fall Time
t
SV
t
C
t
FALL
NPN EPITAXIAL SILICON TRANSISTOR
I
C
=1A, Vclamp=300V, I
B1
=0.2A,
V
BE(OFF)
=5Vdc, T
C
=100℃
1.7
0.29
0.15
4
0.75
μs
μs
μs
Note: Pulse Test : PW=300μs, Duty Cycle≤2%
CLASSIFICATION OF h
FE1
RANK
RANGE
A
8 ~ 16
B
15 ~ 21
C
20 ~ 26
D
25 ~ 31
E
30 ~ 36
F
35 ~ 40
Table 1.Test Conditions for Dynamic Performance
Reverse Bias Safe Operating Area and Inductive Switching
+5V
1N4933
0.001μF
33
MJE210
L
MR826*
Vcc
Resistive
Switching
Test Circuits
5V
P
w
DUTY CYCLE≦10%
t
R
, t
F
≦10ns
1k
68
33 1N4933
2N2222
1k
+5V
1k
2N2905
47
1/2W
MJE200
100
-V
BE
(
OFF
)
R
B
I
B
T.U.T.
Ic
5.1k
51
V
clamp
*SELECTED FOR≣1kV
V
CE
1N4933
0.02μF
270
+125V
Rc
TUT
R
B
D1
-4.0V
SCOPE
NOTE
P
W
and Vcc Adjusted for Desired Ic
R
B
Adjusted for Desired I
B1
Circuit Values
Coil Data :
V
CC
=20V
Ferroxcube core #6656
Vclamp=300V
Full Bobbin ( ~ 200 Turns) #20
GAP for 30 mH/2 A
Lcoil=50mH
V
CC
=125V
R
C
=125Ω
D1=1N5820 or
Equiv.
R
C
=47Ω
Output Waveforms
Test Waveforms
Ic
Ic(pk)
t
t1
tf
tf CLAMPED
t1 Adjusted to
Obtain Ic
t1≒
V
CE
or
Vclamp
TIME
t2
t
Lcoil(Icpk)
Vcc
Test Equipment
Scope-Tektronics
475 or Equivalent
+10.3 V
25μS
0
-8.5V
tr, tf<10ns
Duty Cycly=1.0%
R
B
and Rc adjusted
for desired I
B
and Ic
V
CE
Lcoil(Icpk)
t2≒ Vclamp
Figure 1. Inductive Switching Measurements
I
CPK
90% V
clamp
I
C
t
sv
t
RV
t
c
V
CE
I
B
90% I
B1
10% V
clamp
10%
Icpk 2% Ic
V
clamp
90% Ic
t
FI
t
TI
Table 2. Typical Inductive Switching Performance
Ic
AMP
0.5
Tc
℃
t
sv
μs
1.3
1.6
1.5
1.7
1.8
3
t
RV
μs
0.23
0.26
0.10
0.13
0.07
0.08
t
FI
μs
0.30
0.30
0.14
0.26
0.10
0.22
t
TI
μs
0.35
0.40
0.05
0.06
0.05
0.08
t
c
μs
0.30
0.36
0.16
0.29
0.16
0.28
25
100
25
100
25
100
1
1.5
Time
NOTE: All Data Recorded in the Inductive Switching
Circuit in Table 1
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QW-R209-022,A
MJE13003
SWITCHING TIMES NOTE
NPN EPITAXIAL SILICON TRANSISTOR
In resistive switching circuits, rise, fall, and storage times have been defined and apply to both current and voltage
waveforms since they are in phase. However, for inductive loads, which are common to SWITCHMODE power
supplies and hammer drivers, current and voltage waveforms are not in phase. Therefore, separate measurements
must be made on each waveform to determine the total switching time. For this reason, the following new terms
have been defined.
t
SV
= Voltage Storage Time, 90% I
B1
to 10% Vclamp
t
RV
= Voltage Rise Time, 10 ~ 90% Vclamp
t
FI
= Current Fall Time, 90 ~ 10% I
C
t
TI
= Current Tail, 10 ~ 2% I
C
t
C
= Crossover Time, 10% Vclamp to 10% I
C
An enlarged portion of the inductive switching waveforms is shown in Figure 7 to aid in the visual identity of these
Terms. For the designer, there is minimal switching loss during storage time and the predominant switching power
losses occur during the crossover interval and can be obtained using the standard equation from AN–222:
PSWT = 1/2 V
CC
I
C
(t
C
)f
In general, t
RV
+ t
FI
≈
t
C
. However, at lower test currents this relationship may not be valid.
As is common with most switching transistors, resistive switching is specified at 25℃ and has become a
benchmark for designers. However, for designers of high frequency converter circuits, the user oriented
specifications which make this a “SWITCHMODE” transistor are the inductive switching speeds (t
C
and t
SV
) which
are guaranteed at 100℃.
RESISTIVE SWITCHING PERFORMANCE
Figure 2. Turn-On Time
2
10
7
1
0.7
0.5
Figure 3. Turn-Off Time
t
s
Vcc=125V
Ic/I
B
=5
T
J
=25℃
t
R
Vcc=125V
Ic/I
B
=5
T
J
=25℃
Time, t (£gs)
5
3
2
Time, t (£gs)
0.3
0.2
1
0.7
0.5
0.3
0.2
t
D
@ V
BE(OFF)
=5V
0.1
0.07
0.05
0.03
0.02
0.02 0.03
0.05 0.07 0.1
0.2
0.3
0.5 0.7
10
20
t
F
0.1
0.02 0.03
0.05 0.07 0.1
0.2
0.3
0.5
0.7
1
2
Collector Current, I
C
(A)
Figure 4. Thermal Response
1
0.7
Collector Current, I
C
(A)
D=0.5
0.2
0.1
0.05
0.02
Effective Transient Thermal
Resistance, R(t) (Normalized)
0.5
0.3
0.2
0.1
0.07
0.05
0.03
0.02
0.01
Single Pulse
0.02 0.03
0.05
0.1
0.2 0.3
0.5
1
2
Z
θJC(t)
=r(t) R
θJC
R
θJC
=3.12℃/W Max
D Curves Apply for Power
Pulse Train Shown
Read Time at t1
T
J(pk)
-TC=P
(pk)
P
θJC(t)
P
(PK)
t
1
t
2
Duty Cycle, D=t
1
/t
2
0.01
0.01
3
5
10
20
50
100
200
500
1000
Time or Pulse Width, t (ms)
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MJE13003
SAFE OPERATING AREA INFORMATION
FORWARD BIAS
NPN EPITAXIAL SILICON TRANSISTOR
There are two limitations on the power handling ability of a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
-V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate.
The data of Figure 5 is based on T
C
= 25℃; T
J(pk)
is variable depending on power level. Second breakdown pulse
limits are valid for duty cycles to 10% but must be derated when T
C
≥25℃.
Second breakdown limitations do not
derate the same as thermal limitations. Allowable current at the voltages shown on Figure 5 may be found at any
case temperature by using the appropriate curve on Figure 7.
T
J(pk)
may be calculated from the data in Figure 4. At high case temperatures, thermal limitations will reduce the
power that can be handled to values less than the limitations imposed by second breakdown.
REVERSE BIAS
For inductive loads, high voltage and high current must be sustained simultaneously during turn-off, in most cases,
with the base to emitter junction reverse biased. Under these conditions the collector voltage must be held to a safe
level at or below a specific value of collector current. This can be accomplished by several means such as active
clamping, RC snubbing, load line shaping, etc. The safe level for these devices is specified as Reverse Bias Safe
Operating Area and represents the voltage-current conditions during reverse biased turn-off. This rating is verified
under clamped conditions so that the device is never subjected to an avalanche mode. Figure 6 gives PBSOA
characteristics.
The Safe Operating Area of figures 5 and 6 are specified ratings (for these devices under the test conditions shown.)
Figure 5. Active Region Safe Operating Area
10
5
2
1
0.5
Tc=25℃
0.2
0.1
0.05
0.02
0.01
5
10
20
50
100
200 300
500
0
0
100
200
300
400
500
600
700
800
dc
5.0 ms
10 ms
Figure 6. Reverse Bias Safe Operating Area
1.6
Collector Current, I
C
(A)
Collector Current, I
C
(A)
100μs
1.2
V
BE(OFF)
=9V
0.8
1.0 ms
T
J
≦100℃
I
B1
=1A
Thermal Limit(Single Pule)
Bonding Wire Limit
Second Breakdown Limit
Curves Apply Below Rated
0.4
5V
3V
1.5V
V
CEO
Collector-Emitter Voltage, V
CE
(V)
Collector-Emitter Clamp Voltage,V
CE
(V)
Figure 7. Forward Bias Power Derating
1
Second Breakdown
Derating
0.8
Power Derating Factor
0.6
Thermal
Derating
0.4
0.2
0
20
40
60
80
100
120
140
160
Case Temperature, T
C
(℃)
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QW-R209-022,A
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