Integrated
Circuit
Systems, Inc.
Programmable Frequency Generator for Celeron & PII/III™
Recommended Application:
VIA Apollo Pro 266 style chipset.
Output Features:
•
3 - CPUs @ 2.5V, up to 200MHz.
•
3 - IOAPIC @ 2.5V, ½ PCI frequency
•
9 - PCI @ 3.3V,
•
1 - 48MHz, @ 3.3V fixed.
•
1 - 24/48MHz @ 3.3V
•
2 - REF @ 3.3V, 14.318MHz.
•
3 - AGP @ 3.3V
Features:
•
Programmable ouput frequency.
•
Programmable ouput rise/fall time.
•
Programmable group skew.
•
Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.
•
Watchdog timer technology to reset system
if over-clocking causes malfunction.
•
Uses external 14.318MHz crystal.
•
FS pins for frequency select
•
Provide all system clocks needed when used with a
memory clock fanout buffer like the ICS93718.
Skew Specifications:
•
CPU – CPU: <175ps
•
PCI – PCI: <500ps
•
CPU(early)-PCI: Min = 1.0ns, Max = 2.5ns
•
CPU Cycle to cycle jitter: < 250ps
•
CPU(early)-AGP: Max = 500ps
ICS94227
Pin Configuration
VDDREF
GND
X1
X2
AVDD48
*FS3/48MHz
*FS2/24_48MHz
GND
PCICLK0
PCICLK1
PCICLK2
GND
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
PCICLK7
GND
PCICLK8
*FS1/RATIO_1
*FS0/RATIO_0
AGPCLK0
VDDAGP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0
REF1/FS4*
VDDL
IOAPIC0
IOAPIC1
GND
IOAPIC2
VDDLCPU
GND
CPUCLK0
CPUCLK1
VDDL
GND
CPUCLK2/F
CPU_STOP#*
RESET#
PD*
AVDD
GND
SDATA
SCLK
AGPCLK2
AGPCLK1
GND
48-Pin 300mil SSOP
*
Internal Pull-up Resistor of 120K to VDD
Power Groups
AVDD= Core PLL
AVDD48 = 24, 48MHz and fixed PLL
VDDREF = REF clocks, Xtal
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
Functionality
FS4 FS3 FS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1 FS0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(MHz)
200.00
190.00
180.00
170.00
166.00
160.00
150.00
145.00
140.00
136.00
130.00
124.00
AG P
(MHz)
80.00
76.00
72.00
68.00
66.40
64.00
75.00
72.50
70.00
68.00
65.00
62.00
PCICLK
(MHz)
40.00
38.00
36.00
34.00
33.20
32.00
37.50
36.25
35.00
34.00
32.50
31.00
2
REF (1:0)
CPU
DIVDER
Stop
2
CPUCLK (1:0)
Stop/F
CPUCLK2/F
3
AGPCLK (2:0)
AGP
DIVDER
FS (4:0)
PD#
CPU_STOP#
SDATA
SCLK
Control
Logic
Config.
Reg.
IOAPIC
DIVDER
3
IOAPIC (2:0)
PCI
DIVDER
Stop
9
PCICLK (8:0)
ICS94227
RESET#
RATIO (1:0)
66.67
100.00
118.00
133.33
66.67
66.67
78.67
66.67
33.34
33.33
39.33
33.34
0446B—12/20/02
ICS94227
General Description
The
ICS94227
is a single chip clock solution for desktop designs using the Apollo Pro 266 style chipset. It
provides all necessary clock signals for such a system.
The
ICS94227
belongs to ICS new generation of programmable system clock generators. It employs serial
programming I
2
C interface as a vehicle for changing output functions, changing output frequency, configuring
output strength, configuring output to output skew, changing spread spectrum amount, changing group divider
ratio and dis/enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which
will reset the frequency to a safe setting if the system become unstable from over clocking.
Pin Descriptions
PIN NUMBER
1, 15, 24
2, 12, 19, 25,
30, 36, 40, 43
3
4
5
6
7
PIN NAME
VDD
GND
X1
X2
AVDD48MHz
FS3
1, 2
48MHz
FS2
1, 2
24_48MHz
AGND48MHz
TYPE
DESCRIPTION
P W R Power supply, nominal 3.3V
PWR
IN
OUT
PWR
IN
OUT
IN
OUT
PWR
OUT
IN
OUT
IN
OUT
OUT
IN
I/O
PWR
IN
OUT
IN
OUT
PWR
OUT
OUT
IN
OUT
OUT
Ground
Cr ystal input, has inter nal load cap (36pF) and feedback
resistor from X2
Cr ystal output, nominally 14.318MHz. Has inter nal load
cap (36pF)
Power for 24 & 48MHz output buffers and fixed PLL core.
Frequency select pin. Latched Input. Internal Pull-up to VDD
48MHz output clock
Frequency select pin. Latched Input. Internal Pull-up to VDD
24 or 48MHz output
Ground for 24 & 48MHz output buffers and fixed PLL core.
PCI clock outputs. Syncheronous to CPU clocks with 1-2ns
skew
Frequency select pin. Latched Input. Internal Pull-up to VDD
Output to chipset, replacing the BSEL signals orginally from
the processor.
Frequency select pin. Latched Input. Internal Pull-up to VDD
Output to chipset, replacing the BSEL signals orginally from
the processor.
AGP outputs defined as 2X PCI. These may not be stopped.
Clock input of I
2
C input, 5V tolerant input
Data pin for I
2
C circuitr y 5V tolerant
Power for PLL core 3.3V
Asynchronous active low input pin used to power down the
device into a low power state. The inter nal clocks are
disabled and the VCO and the cr ystal are stopped. The
l a t e n c y o f t h e p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s.
Real time system reset signal for frequency value or watchdog
timmer timeout. This signal is active low.
This asynchronous input halts CPUCLKs at logic "0" level
when driven low.
CPUCLK either stoppable through CPU_STOP# or free
running depending on I
2
C selection , 0 = Free Running 1=
Stoppable
Supply for CPU & IOAPIC clocks 2.5V nominal
CPU clock outputs, Low if CPU_STOP#=Low
IOAPIC c l o ck o u t p u t , @ ½ P C I f r e q u e n c y. Powe r e d by
VDDL.
Frequency select pin. Latched Input
14.318 MHz reference clock.
14.318 Mhz reference clock.
8
20, 18, 17, 16, 14,
PCICLK (8:0)
13, 11, 10, 9
FS1
1, 2
21
RATIO_1
FS0
1, 2
22
27, 26, 23
28
29
31
32
33
34
35
37, 41, 46
38, 39
42, 44, 45
47
48
RATIO_0
AGPCLK (2:0)
SCLK
SDATA
AVDD
PD#
1
RESET#
CPU_STOP#
1
CPUCLK2/F
VDDL
CPUCLK (1:0)
I OA P I C ( 2 : 0 )
FS4
1, 2
REF1
REF0
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
0446B—12/20/02
2
ICS94227
General I
2
C serial interface information for the ICS94227
How to Write:
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending
Byte 0 through Byte 20
(see Note)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends
Byte 0 through byte 8 (default)
ICS clock sends
Byte 0 through byte X (if X
(H)
was
written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address D2
(H)
Dummy Command Code
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address D3
(H)
ICS (Slave/Receiver)
ACK
ACK
Dummy Byte Count
ACK
Byte Count
ACK
Byte 0
ACK
ACK
Byte 0
Byte 1
ACK
ACK
Byte 1
Byte 2
ACK
ACK
Byte 2
Byte 3
ACK
ACK
Byte 3
Byte 4
ACK
ACK
Byte 4
Byte 5
ACK
ACK
Byte 5
Byte 6
ACK
ACK
If 7
H
has been written to B6
ACK
Byte 6
Byte 7
ACK
Byte 18
ACK
Byte 19
ACK
Byte 20
ACK
Stop Bit
*See notes on the following page
.
0446B—12/20/02
If 12
H
has been written to B6
ACK
If 13
H
has been written to B6
ACK
If 14
H
has been written to B6
ACK
Stop Bit
Byte18
Byte 19
Byte 20
3
ICS94227
Brief I
2
C registers description for ICS94227
Programmable System Frequency Generator
Register Name
Functionality &
Frequency Select
Register
Output Control Registers
Byte
0
Description
Output frequency, hardware / I C
frequency select, spread spectrum &
output enable control register.
Active / inactive output control
registers/latch inputs read back.
Byte 11 bit[7:4] is ICS vendor id -
1001. Other bits in this register
designate device revision ID of this
part.
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00
H
to
this byte.
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
Watchdog enable, watchdog status
and programmable 'safe' frequency'
can be configured in this register.
This bit select whether the output
frequency is control by
hardware/byte 0 configurations or
byte 11&12 programming.
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
These registers control the spread
percentage amount.
Increment or decrement the group
skew amount as compared to the
initial skew.
These registers will control the
output rise and fall time.
2
PWD Default
See individual
byte
description
See individual
byte
description
See individual
byte
description
1-6
Vendor ID & Revision ID
Registers
7
Byte Count
Read Back Register
8
08
H
Watchdog Timer
Count Register
9
10
H
Watchdog Control
Registers
10 Bit [6:0]
000,0000
VCO Control Selection
Bit
10 Bit [7]
0
VCO Frequency Control
Registers
11-12
Depended on
hardware/byte
0 configuration
Depended on
hardware/byte
0 configuration
See individual
byte
description
See individual
byte
description
Spread Spectrum
Control Registers
Group Skews Control
Registers
Output Rise/Fall Time
Select Registers
13-14
15-16
17-18
1.
2.
3.
4.
5.
6.
7.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol.
The number of bytes to
readback is defined by writing to byte 8.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set.
If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
0446B—12/20/02
4
ICS94227
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Description
Bit 2 Bit 1 Bit 6 Bit 5 Bit 4 CPUCLK AGPCLK PCICLK
(MHz)
(MHz)
(MHz)
FS4 FS3 FS2 FS1 FS0
0
0
0
0
0
200.00
80.00
40.00
0
0
0
0
1
190.00
76.00
38.00
0
0
0
1
0
180.00
72.00
36.00
0
0
0
1
1
170.00
68.00
34.00
0
0
1
0
0
166.00
66.40
33.20
0
0
1
0
1
160.00
64.00
32.00
0
0
1
1
0
150.00
75.00
37.50
0
0
1
1
1
145.00
72.50
36.25
0
1
0
0
0
140.00
70.00
35.00
0
1
0
0
1
136.00
68.00
34.00
0
1
0
1
0
130.00
65.00
32.50
0
1
0
1
1
124.00
62.00
31.00
0
1
1
0
0
66.67
66.67
33.34
0
1
1
0
1
100.00
66.67
33.33
0
1
1
1
0
118.00
78.67
39.33
Bit 2,1
Bit 6:4
0
1
1
1
1
133.33
66.67
33.34
1
0
0
0
0
66.80
66.80
33.40
1
0
0
0
1
100.20
66.80
33.40
1
0
0
1
0
115.00
76.67
38.33
1
0
0
1
1
133.40
66.70
33.35
1
0
1
0
0
66.80
66.80
33.40
1
0
1
0
1
100.20
66.80
33.40
1
0
1
1
0
110.00
73.33
36.67
1
0
1
1
1
133.40
66.70
33.35
1
1
0
0
0
105.00
70.00
35.00
1
1
0
0
1
90.00
60.00
30.00
1
1
0
1
0
85.00
56.67
28.33
1
1
0
1
1
78.00
78.00
39.00
1
1
1
0
0
66.67
66.67
33.34
1
1
1
0
1
100.00
66.67
33.33
1
1
1
1
0
75.00
75.00
37.50
1
1
1
1
1
133.33
66.67
33.34
0 - Frequency is selected by hardware select, Latched Inputs
Bit 3 1 - Frequency is selected by Bit 2,1 (6:4)
Bit 7 0 - Normal
1 - Spread Spectrum Enabled
Bit 0 0 - Running
1- Tristate all outputs
Bit
PWD
IOAPIC
(MHz)
20.00
19.00
18.00
17.00
16.60
13.00
18.75
18.12
17.50
17.00
16.25
15.50
16.67
16.66
19.66
16.67
16.70
16.70
19.16
16.67
16.67
16.70
18.33
16.67
17.50
15.00
14.16
19.5
16.67
16.66
18.75
16.67
Spread
Precentage
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.75%
+/- 0.75%
+/- 0.25%
+/- 0.75%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.5%
+/- 0.5%
+/- 0.25%
+/- 0.5%
+/- 0.25%
+/- 0.25%
+/- 0.25%
+/- 0.25%
0 to -0.5%
0 to -0.5%
+/- 0.25%
0 to -0.5%
XXXX
Note1
0
1
0
Note1: Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3.
0446B—12/20/02
5
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